The driver sets the search lines to an N-bit value to search for in the CAM.
所述驱动器将所述搜索线设定为用以在所述CAM中搜索的N位值。
Through controlling an N-bit accumulator and then get its highest bit to generate the programmable clock.
通过控制一个N位累加器累加，取其最高位，即可得到可编程时钟源。
Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.
该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。
The driving component includes: a N-bit serial buffer, a K-bit extension buffer, a N-bit video data buffer and N driving current output ports.
该驱动元件包括：一N个位的串序缓冲器，一K个位的延伸缓存器，一N个位的影像资料缓存器，N个驱动电流输出端口。
The first selected element selects two voltage references from the first group of voltage references according to m most significant bits of the N-bit digital signal.
第一选择单元依据N位数字信号的M个最高位，由第一组参考电压中选择出两参考电压。
The second selected element selects one of the second groups of voltage references as an output analog voltage according to N-M least significant bits of the N-bit digital signal.
第 二选择单元依据N位数字信号的N-M个最低位，选择第二组参考电压之一作为输出模拟电压。
For a given n-bit positive integer a and positive integer k, to design an algorithm to identify the composition of the remaining number of the smallest number of new programs to delete a few.
对于给定的n位正整数a和正整数k，设计一个算法找出剩下数字组成的新数最小的删数方案。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
No, just a bit more complicated-it's M-A-U-G-H-A-N.
不，只是稍微复杂一点，是 M-A-U-G-H-A-N。
I won 't forgive myself for that mistake I made, for that little bit of cockiness n.
我不会原谅我犯下的错，因为我的骄傲自大而认为她配不上我。
N you know, Brian, it sounds a bit odd, you have never told me before.
你知道么，Brian，这听起来有点奇怪，你从未告诉过我这些。
Note: The actual bitn, the 512-bit n is not secure, it is recommended that companies with 1024-bitn, and the important occasion with a 2048-bitn.
注：实际应用中，512比特的n 已经不够安全，所以建议公司用1024比特的n，及其重要的场合用2048比特的 n。
The accelerator is implemented with multiple levels of bit manipulator instead of MUX, it reduces the time complexity of the accelerator from o (n) to o .
该方法通过使用分层位操作电路取代分层MUX选择电路实现位操作加速来减少电路时延，使得位操作加速器的时间复杂度从o (N)降到了O 。
For each case, output sum (n) in one line, followed by a blank line. You may assume the result will be in the range of 32-bit signed integer.
对于每一种情况，SUM在空白行之后的单独的一行输出。假定所有的结果都在有符号的32位整型范围之内。
Thus, tuning can be accomplished via a 2-byte serial transfer to the 16-bit N register.
因此通过16比特N寄存器的2字节串行转换，调谐就可以实现。
Thus, tuning can be accomplished via a 2-byte serial transfer to the 16-bit N register.
因此通过16比特N寄存器的2字节串行转换，调谐就可以实现。
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