A solution for property verification of synchronous VHDL design is introduced, and VERIS an efficient symbolic model checker is implemented.
介绍了一个针对同步时序电路VHDL设计的性质验证的解决方案——一个有效的符号模型判别器veris。
Decision diagram model is a utility to represent data dependence between signals in VLSI designs, and is widely used in VLSI design verification.
决策图模型描述了VLSI设计信号间的数据依赖关系，在VLSI设计验证中有广泛的应用。
By the verification of error analysis, the accuracy and reliability of the model accord with the designing demands, and can be used by the production and design units.
经过误差分析验证，模型的精度、可靠度均满足设计要求，可供生产设计单位使用。
C model was applied to build simulation stimulus and expected output responses, and reusable verification structure and verification method of Grey-box were also applied to this design.
通过C仿真模型来创建仿真激励和期望响应，采用了可重用的验证结构和灰盒的验证方法。
A method and system for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification.
一种用于通过仿真全阵列模型中的边缘单元的操作来检验阵列性能的方法和系统，其减少了用于完整的设计检验所需的计算时间。
A method and system for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification.
一种用于通过仿真全阵列模型中的边缘单元的操作来检验阵列性能的方法和系统，其减少了用于完整的设计检验所需的计算时间。
应用推荐