In deep sub - micron technology, the mount of the static power catches up with the dynamic power gradually and the standby power is becoming an important factor in low power design.
进入深亚微米工艺后，静态功耗开始和动态功耗相抗衡，已成为低功耗设计一个不可忽视的因素。
In this paper, design technologies of sub-micron CMOS gate array, such as building library, testability, clock design, power-ground design, architecture optimizing, margin design, are presented.
本文主要论述亚微米cmos门阵列的设计技术，包括建库技术，可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等，最后给出了应用实例。
It USES two power supplies to supply power to digital part and analog part. It USES the Hejian Technology 0.18-micron technic.
采用双电源分别为数字模块和模拟模块供电，采用和舰科技0.18微米工艺。
As the semiconductor manufacturing process technology into the deep sub-micron or even nanometer, power consumption is becoming increasingly prominent.
随着集成电路工艺制程进入超深亚微米甚至纳米级，集成电路的功耗问题显得日益突出。
As the semiconductor manufacturing process technology into the deep sub-micron or even nanometer, power consumption is becoming increasingly prominent.
随着集成电路工艺制程进入超深亚微米甚至纳米级，集成电路的功耗问题显得日益突出。
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