A pulse to gate the output of a core memory sense amplifier into a trigger in a register.
将磁心存储器读出放大器的输出选通到寄存器的触发器中的一种脉冲。
Sense Amplifier is nowadays widely used in the memory system design, IO design to improve speed.
灵敏放大器广泛地应用于存储器系统和IO设计中。
A novel current mode sense amplifier with high read-speed for non-volatile memory application is developed.
对此，设计出一种具有较快读取速度的新型电流灵敏放大器。
In various embodiments of the invention, a memory device includes at least one sense amplifier with an asymmetrical configuration.
在本发明的各实施例中，一种存储装置包含呈不对称配置的至少一个检测放大器。
The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines.
该半导体存储器件包含连接到一对位线的位线感测放大器。
The state of the memory element can thereby be detected by a voltage comparator sense amplifier that is connected to the bit line.
因此可通过连接到位线的电压比较器读出放大器来检测存储器元件的状态。
The whole circuit includes memory array, decode, sense amplifier, data in - out circuit and pre - charge circuit.
电路包括存储阵列、译码电路、敏感放大器、数据输入输出电路，预充电电路等部分。
The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer.
其中包括地址缓冲、译码器、存储单元、灵敏放大器和输出缓冲电路。
A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided.
从某种意义上说放大器控制信号产生的半导体存储器设备电路提供。
A fast access time is achieved by using six-transistor CMOS memory cell, latched sense amplifier, and high-speed decoder circuit.
存储器采用六管CMOS存储单元、锁存器型敏感放大器和高速译码电路，以期达到最快的存取时间。
A sense amplifier circuit for reading the state of memory cells.
本发明提供一种用于读取存储器单元的状态的读出放大器电路。
This paper describes computer-aided design of a sense amplifier circuit in a magnetic core memory. The sense amplifier circuit has been modified by analyzing its threshold characteristic.
本文概要地介绍了计算机辅助一种磁芯读放电路的改进设计，解析了读放电路的门槛特性，阐明了利用电路分析系统DFX-1对该电路的分析与设计。
This paper describes computer-aided design of a sense amplifier circuit in a magnetic core memory. The sense amplifier circuit has been modified by analyzing its threshold characteristic.
本文概要地介绍了计算机辅助一种磁芯读放电路的改进设计，解析了读放电路的门槛特性，阐明了利用电路分析系统DFX-1对该电路的分析与设计。
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