This Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoders using traditional trace-back methods.
与采用传统回溯法的译码器相比，该译码器具有较低的译码时延、有效的存储空间管理和较低的硬件复杂度。
The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer.
其中包括地址缓冲、译码器、存储单元、灵敏放大器和输出缓冲电路。
The FPGA is designed as a MVB controller which consists of Manchester encoder, Manchester decoder, buffer, center control unit, internal memory, MCU interface and so on.
FPGA实现MV B控制器功能，分为曼彻斯特编码器、解码器、缓冲区、中央控制单元、内部存储器和单片机接口等几部分。
A video interface design based on XCV300FPGA is introduced. The implementations of video-in decoder and memory DAC video-out are discussed in detail.
介绍了一种以xcv300 FPGA为核心的视频接口设计。同时按照视频输入、解码存储、DAC转换输出视频流的流动顺序，给出了实现方法。
Coder, decoder its method, data processing system, memory medium and signal.
编码装置、解码装置及方法，数据处理系统，存储介质及信号。
A fast access time is achieved by using six-transistor CMOS memory cell, latched sense amplifier, and high-speed decoder circuit.
存储器采用六管CMOS存储单元、锁存器型敏感放大器和高速译码电路，以期达到最快的存取时间。
Decoder is one of the most important components in a memory unit, and its improvement can greatly diminish the access time of both register file and SRAM.
译码器是存储部件关键路径的重要组成部分，提高译码速度能有效提高寄存器文件和SRAM的读写速度。
Chapter 3 presents the design and implementation of memory management of RTOS for the HDTV integrated source decoder chip.
第三章具体描述应用于HD TV信源解码芯片的实时操作系统存储管理策略的设计及实现。
In this paper, a novel high-density address decoder architecture is proposed to avoid memory array's lateral conducting current in reading and programming mode.
论文中设计了一种高密度的译码器电路架构，同时针对阵列提出了解决读取和编程时存在的阵列横向导通电流问题。
In this paper, a novel high-density address decoder architecture is proposed to avoid memory array's lateral conducting current in reading and programming mode.
论文中设计了一种高密度的译码器电路架构，同时针对阵列提出了解决读取和编程时存在的阵列横向导通电流问题。
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