The increased data bus width enables support for addressable memory space above the 4gb generally available on 32bit architectures.
增加的数据总线带宽实现了对32位架构上通常可用的4gb以上可寻址内存空间的支持。
A memory address consists of binary data being output on an appropriate bus which we call the address bus.
一个存储器地址是由输出到适宜的总线上的二进制数据所组成。这个总线我们称为地址总线。
Because most devices are separated from the CPU by a bus, which is much slower to send data across than it is to write to CPU registers or (cached) memory.
因为大多数设备是分开的CPU总线，慢得多的发送数据跨比写信给CPU寄存器或内存(缓存)。
The memory structure, constitution of data communication channel and system bus are analyzed, and the algorithm allocating, algorithm mapping and scheduling on the multiprocessor are discussed.
对系统的存储器结构、数据通信通道组成和系统总线结构进行了分析； 讨论了算法划分、算法的多处理器映射及调度；
This is necessary to avoid loading redundant data and therefore to use the video memory bandwidth and that of the AGP bus as efficiently as possible.
另外，为了尽可能高效的利用显存的带宽和AGP总线带宽，应该极力避免载入冗余数据。
Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory.
端口0也是复低位地址和在利用外部程序和数据存储器的数据总线。
The particular memory location and data value that must be written are selected by the host's bus manager, it can't just be any an arbitrary value.
特定的内存位置和数据值必须被写入由主机的总线管理器选择，不可能仅仅是一个任意值。
With time series simulation software, the CPU's I/O ports simulate I2C bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices.
采用软件模拟时序使CPU的I/O口模拟I2C总线，实现了单片机与时钟芯片、温湿度传感器、存储芯片等器件的数据交换。
The dual-ported RAM is a kind of special memory, and the bus data share between double high-speed microprocessors is carried out by using it.
双端口ram是一种特殊的数据存储芯片，利用双端口ram可以实现双高速单片机总线方式的数据共享。
This type of bus interface can be accessed by memory mode and be applied to the exchange of data between two hosts, which can overcome the lack of communication interface in some types of CPU.
本接口采用存储器访问模式，克服了某些CPU外围通信接口少的缺点，易于实现双CPU间的总线对接，且无需考虑复杂的总线仲裁机制。
The address bus specifies the memory locations (addresses) for the data transfers.
地址总线为数据传输指明内存位置(地址)。
To a micro-controller, the PDIUSBD12 appears as a memory device 8-bit data bus and 1 address bit (occupying 2 locations).
对微控制器而言，PDIUSBD12看起来就像一个带8位数据总线和一个地址位（占用两个位置）的存储器件。
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data.
数据总线上的输入数据是否写入存储器，取决于此时的DM的输入逻辑。
This high-speed data acquisition card designed is based on PCI bus and have high capacity memory interface. It combines high-speed date acquisition and high capacity real-time memory.
为此，本文设计了一款基于PCI总线且具备可扩展大容量存储设备接口的高速模拟信号采集卡，将高速数据采集和大容量实时存储结合在一起。
In data storage transmission modular, we adopt PCI bus line and FIFO data memory carry out succession for plenty of data to storage transmission, guarantee AE signal accurate collecting.
数据存储传输模块采用PCI总线和FIFO数据存储器对大量的数据进行连续存储传输，保证数据的准确完整。
Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。
Based on the designed PCI bus memory card, the signal definitions and command operations of PCI bus and the process of data access on the PCI bus are discussed in detail.
以自行开发的PCI总线存储卡为背景，详细论述了PCI总线的信号定义和命令操作，以及总线上的数据传输过程。
The memory system of dual channel A/D automatic acquisition is studied in this paper. Using transceivers and gating controllers, the data bus and address bus of RAM are respectively controlled.
本文研究了双通道A/D自动采集存储系统，利用数据收发器及数据选通控制器分别控制RAM的数据线及地址控制线。
It realizes the dynamic monitoring, condition information memory, re-play and warning etc. to the spot signal devices by use of the advanced spot bus, sensors, web techniques, data base.
它采用先进的现场总线、传感器、计算机网络技术，利用数据库等软件工程，对现场信号设备实施动态监测，状态信息储存、重放和报警等。
It realizes the dynamic monitoring, condition information memory, re-play and warning etc. to the spot signal devices by use of the advanced spot bus, sensors, web techniques, data base.
它采用先进的现场总线、传感器、计算机网络技术，利用数据库等软件工程，对现场信号设备实施动态监测，状态信息储存、重放和报警等。
应用推荐