Does it contain memory access errors?
是否包括内存访问错误？
This is the purpose behind the user space memory access functions.
这就是用户空间内存访问函数的目的。
The user space memory access functions to be explored are listed in Table 1.
用户空间内存访问函数在表1中列出。
To enable memory access, it provides put and set methods for ints, chars, and bytes.
为允许内存访问，它为int、char和byte提供了put 和set方法。
Some types of memory access errors (like using a NULL pointer) cause a program to crash outright.
有些类型的内存访问错误 (比如使用一个NULL指示器) 将会导致一个程序完全崩溃。
But it causes the problem of memory access wait cycle.
但随之带来了访问内存时出现等待周期的问题。
External memory access requests are processed by first reading the corresponding security bit.
外部存储器存取请求首先通过读取相应的安全位来处理。
The database will be slower than the memory access, so two servers will not be twice as fast as one.
数据库访问比内存访问慢，所以两台服务器的处理速度达不到一台服务器的两倍。
Purify adds value to your existing correctness tests by simultaneously checking for memory access errors.
Purify 可以通过同时检查内存访问错误来对您的现存正确性测试增加价值。
The index register is added to the specified address, and the result is used as the address for the memory access.
索引寄存器会与某个指定的地址相加，结果用作访问内存时使用的地址。
Large page usage is primarily intended to provide performance improvements to memory access intensive applications.
使用大页主要是为提高内存访问频繁的应用程序的性能。
In this paper, we propose a performance analysis method on the study for instruction stream and memory access.
本文基于指令执行流和内存访问流的分析，提出一种性能分析的新方法。
Thus, it is more important to provide continuous data stream than to reduce the delay of single memory access.
因此，向处理器内核提供连续的数据流比降低单个存储访问的延迟更加重要。
Your write system call will be interrupted by the bus error signal SIGBUS, because you performed a bad memory access.
此时write系统调用会被进程接收到的SIGBUS信号中断，因为当前进程访问了非法内存地址。
Thus, how to improve memory access performance has been an important direction in computer architecture research.
因此，如何提高访存性能已经成为计算机体系结构研究的一个重要方向。
Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.
因此研究系统总线协议及其实现技术对于隐藏访存延迟和提高访存速度具有重要意义。
Memory needs and memory access times are reduced by computing intermediate results by stages and decreasing temporary results storage.
分阶段计算中间结果，减少临时结果存储，可减小存储器需求和存储器访问次数。
Software pipelining has been combined with several memory optimization technologies for higher performance by hiding memory access latency.
为了减轻存储系统影响，软件流水结合了一些存储优化技术，通过隐藏存储延迟来提高性能。
Moreover, to design a storage scheme for both memory access conflict free and network alignment conflict free is also a NP Complete problem.
另外设计同时满足存储访问无冲突和互联网络无冲突的存储方案设计问题也是一个NP完全问题。
When AME is enabled for an LPAR, the operating system starts compressing and decompressing data in memory based on the workload's memory access pattern.
在为LPAR启用AME时，操作系统将开始根据工作负载的内存访问模式压缩和解压缩内存中的数据。
Therefore, the amount of time required for any particular memory access is completely unknown (if the memory is swapped out, who knows how long it will take).
因而，某一内存访问所需的时间是完全未知的(如果内存被换出，所需时间的长短是不可知的)。
The other main type of processor architecture, CISC (the x86 processor being a popular CISC instruction set), allows for memory access in nearly every instruction.
另外一种主要的处理器体系结构CISC (x86处理器就是一种流行的CISC指令集)几乎允许在每条指令中进行内存访问。
Any memory access that is not available by other modes (the address can be calculated by other means and stored in the register, which is then used for the access).
使用其他模式无法进行的内存访问(地址可以通过其他方式进行计算，并存储到寄存器中，然后就使用这个值来访问内存)。
The register indirect addressing mode uses a register to specify the whole address for the memory access. This is used for numerous situations, including, but not limited to
寄存器间接寻址模式使用一个寄存器来指定内存访问的整个地址。
The tightly-coupled nature of the CMP allows very short physical distances between processors and memory and, therefore, minimal memory access latency and higher performance.
CMP紧密耦合的本质使处理器与内存之间的物理距离很短，因此可提供最小的内存访问延迟和更高的性能。
The first copy (see Figure 1) is performed by the direct memory access (DMA) engine, which reads file contents from the disk and stores them into a kernel address space buffer.
直接内存存取(direct memory access,DMA)引擎执行了第一次拷贝(参见图1)，它从磁盘中读取文件内容，然后将它们存储到一个内核地址空间缓存区中。
CICS TG on z/OS makes use of the EXCI to provide high speed cross memory access to CICS, a mechanism not available on other platforms as it is an MRO-based communications mechanism.
z/OS上的CICSTG使用EXCI提供对 CICS 的高速交叉存储访问，这是其他平台无法提供的机制，因为它是基于MRO 的通信机制。
Because workloads with high Symmetrix cache read-hit rates are serviced at memory access speed, storing the data needed on EFDs may not result in a significant increase in performance.
因为具有高symmetrix缓存读中率的工作负载都是以内存访问速度实现的，所以在EFD中存储所需要的数据可能不会对性能有大的改进。
With the processor-memory performance gap continuing to grow, the performance of memory access becomes the major bottleneck of the performance improvement for modern microprocessors.
随着存储系统的访问速度与处理器的运算速度的差距越来越显著，访存性能已成为提高计算机系统性能的瓶颈。
The functional coverage model was set up based on on-chip-debugging structure features and the virtual verification prototype was built steadily according to the different memory access modes.
根据在片调试的结构特征建立了功能覆盖率模型，并以访存模式为基准分步建立虚拟验证原型。
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