Near the end of the expansion phase, the ring of plasma breaks open, and some of the plasma appears to escape the pull of the magnetic field loop.
在日珥的扩张接近结束时，等离子体构成的圆环猛然裂开，一些等离子似乎要挣脱磁场拉力的束缚。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
The result proved that the cancellation performance of cancellation loop is decided by the amplitude imbalance, phase imbalance and delay mismatch.
指出环路的抑制性能是由前馈环的延迟失配、幅度失配和相位失配共同决定。
Using multi loop analysis method, the dynamic characteristics of ac excited generator are analyzed based on phase coordinate.
采用多回路的分析方法，对建立在相坐标下的交流励磁发电机的动态性能进行了分析。
In the new scheme proposed, the phase lock loop is avoided and the digital logical circuit is used.
该方案利用信号自身的特性，采用数字逻辑设计，有效避免了性能不高的锁相环的使用。
In frequency synthesis by phase lock, the loop gain will vary by the same amount due to this effect, which generally im - pedes optimization of loop performance.
在锁相频率合成器中，由于压控灵敏度的变化，环路增益也将产生同样大小的变化，这就妨碍了环路特性的最佳化。
Because of the fading characteristic in troposcatter channel, the mechanism of traditional phase locked loop is difficult to achieve the effect in troposcatter communication.
由于对流层散射信道存在严重的衰落现象，故而传统的锁相环机制在散射通信中往往难以奏效。
Anovel approach to implement symbol timing recovery is presented which USES a hybrid digital phase locked loop (HDPLL).
本文介绍了一种利用混合数字锁相环(HDPLL)实现码元定时恢复的新方法。
Phase-locking loop circuit, phase shifting method, and IC chip.
锁相环电路，相移方法，及集成电路芯片。
The circuits used are Chua 'circuit and phase lock loop.
所用的电路为蔡氏电路和锁相环电路。
Digital phase lock loop is a key part of the digital demodulator.
数字锁相环是数字解调器的关键部件。
The method of designing the loop filter with the phase margin and loop bandwidth is displayed.
并提出了从环路带宽和相位余量出发设计环路滤波器的方法。
Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).
然后介绍了锁相环(PLL)的基本结构、相位模型、频率响应、噪声及杂散性能。
This design is the use of leading correction principle, finally meet the performance index of a control system open loop gain, phase margin, angular frequency requirements.
本设计利用超前校正原理，最终满足对控制系统性能指标开环放大系数、相角裕量、截止角频率的要求。
According to transfer functions of the loop filter and the single phase locked loop system, it figures out the loop filters parameters, and introduces the selection of loop bandwidth.
根据环路滤波器传递函数以及单环锁相系统的传递函数，计算出环路滤波器的各个参数，并介绍了环路带宽的选择。
This paper proposes a carrier phase tracking loop dedicated for VSB demodulation.
本文提出了一种专门用于数字VSB解调的载波相位跟踪环。
This paper puts forward a voltage and current double closed-loop controlling method based on three-phase voltage source PWM inverter.
提出了一种基于三相电压型PWM逆变器的电压电流双闭环控制方法。
An automatic accurate synchronization control scheme which adopts phase locked loop principle is presented.
利用锁相环路原理提出锁相自动准同期控制方案。
The primary factor affecting fast phase lock is analyzed by using MATLAB. Then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.
应用MATLAB分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
This paper introduces a method of FSK modulation and demodulation using CMOS phase locked-loop chip CD4046.
文章介绍了一种利用CMOS锁相环芯片CD 4046实现FSK信号调制与解调的方法。
The possibility of using this kind of phase-locked loop under noise interference and the problems of filter design are discussed.
文中还讨论了在噪声作用下采用这种环路的可能性和滤波器的设计问题。
A fast all digital phase-locked loop with automatic modulus control is presented.
提出了一种具有自动变模控制的快速全数字锁相环。
In phase-coherent communication system, phase-locked loop is always used to yield coherent reference signal.
相位相干通信系统中，通常采用锁相环路来产生相干参考信号。
The design and implementation of quadrature waveform generator are described based on the AT89C52, phase-locked loop(PLL) and switched-capacitor filter(SCF).
描述了基于AT89C52单片机、锁相环和开关电容滤波器的正交信号发生器的设计和实现方法。
In the process of signal digital intermediate-frequency received, digital down convertion, frequency tracking of carrier and phase locked loop are the keys.
在信号的中频数字接收过程中，数字下变频、载波频率与相位跟踪是设计的关键所在。
In this thesis the basic architecture and the performance evaluation of phase-locked loop are presented.
本文研究了锁相环的基本结构与系统构架及其性能优劣。
In the experiment, the feasibility of the digital control is validated for amplitude and phase close loop operation in driven mode.
通过实测，验证了他激模式下幅度控制环路和相位控制环路中实现数字式控制的可行性。
The phase- locked loop is one kind of control system which is able to achieve phase automatic lock, to compose frequency and to trace demodulation system.
锁相环路是一种能实现相位自动锁定的控制系统，主要用于频率合成及跟踪解调系统。
The phase- locked loop is one kind of control system which is able to achieve phase automatic lock, to compose frequency and to trace demodulation system.
锁相环路是一种能实现相位自动锁定的控制系统，主要用于频率合成及跟踪解调系统。
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