Each application is bound to its own logical bus.
每个应用绑定到它自己的逻辑总线上。
This pattern suggests four levels of interest in a federated service bus infrastructure consisting of multiple logical buses.
这个模式在一个由多个逻辑总线组成的联邦服务总线基础设施中划出了4个关注级别。
Figure 3 depicts such a logical architecture where the service providers and service consumers communicate through a logical bus.
图3描述了一个这样的逻辑体系结构，其中的服务提供者和服务使用者通过逻辑总线进行通信。
The consumers communicate with the logical bus, which keeps track of the available services from the providers, and in turn calls the appropriate provider.
使用者与逻辑总线进行通信，而后者跟踪来自提供者的可用服务，并负责调用恰当的提供者。
A Service Integration Bus (SIB) is a logical concept.
服务集成总线(SIB)是一个逻辑概念。
A destination is the logical target for each message that is sent to the bus.
目的地是每一条发送到总线上的消息的逻辑目标。
On a write, the DIF is generated by the host bus adapter (HBA), based on the block data and logical block address.
在写数据时，主机总线适配器(HBA)根据块数据和逻辑块地址生成dif。
The first three numbers for each item refer to SCSI bus, device ID, and LUN (Logical Unit Number), respectively.
每一项的前三个数字分别指SCSI总线、设备标识和LUN（逻辑单元号，Logical Unit Number）。
However, here we can define the Service Integration BUS (simply BUS later) as a logical cloud, that provides the mechanisms to interconnect a consumers with a providers. This logical cloud contains.
然而，我们可以定义服务集成总线(后面简称为总线)为一个逻辑云，其可以提供消费者与提供商互连的机制。
The hypervisor ensures that each logical partition can access only the PCI slots assigned to it and not other PCI devices, even if they are on the same bus.
Hypervisor可以确保每个逻辑分区仅能够访问分配给它的pci插槽，而不能访问其他PCI设备，即使它们处于相同的总线。
However, the bus object that runs on the web server dispatches each of these logical messages one at a time to the message handler above.
而Web服务器上的bus对象则每次只会向如上的消息处理器发出一条逻辑消息。
Jack presents a logical approach to modeling the service bus infrastructure.
Jack给出了一种服务总线基础设施的建模方法。
The maintenance algorithm must be invoked, if the logical ring of the token bus LAN is broken.
在令牌总线局域网络中，当逻辑环被破坏时，就要运行逻辑环维护算法。
When it connects to ARM, driving circuits (sequential logical circuits) is necessary because CMOS star sensor doesn't belong to I2C bus circuits.
CMOS敏感器不是I2C总线电路，因此同arm连接必须有驱动电路(时序逻辑电路)。
The effective maintenance algorithm for logical ring plays an important role in keeping the network real -time. The complexity of algorithm is the main barrier of implementing the token bus LAN.
逻辑环维护算法的效率是影响网络实时性的重要因素，也是令牌总线局域网络投入实用的主要难点。
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.
该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制，通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.
该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制，通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
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