Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data.
数据总线上的输入数据是否写入存储器，取决于此时的DM的输入逻辑。
The input voltage at which the output logic level changes state.
输出逻辑电平改变状态时的输入电压。
The input voltage at which the output logic level changes state.
输出逻辑电平改变状态时的输入电压。
应用推荐