A special testing sequence input is need for measuring maximum dyna - mic current of a combinational logic circuit.
组合逻辑电路的最大动态电流测试应在电路的原始输入端施加一个特定的测试序列才能实现。
The digital logic chip of the invention and the method of design for testing can realize the observation of circuit scanning test by adopting few pins.
本发明的数字逻辑芯片及其可测试设计的方法，能够通过少量管脚实现电路在扫描测试时的可观测。
The digital logic chip of the invention and the method of design for testing can realize the observation of circuit scanning test by adopting few pins.
本发明的数字逻辑芯片及其可测试设计的方法，能够通过少量管脚实现电路在扫描测试时的可观测。
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