The use of phase-locked loop technology makes the sampling frequency synchronously follow the signal frequency and improves the calculation accuracy of sampling data.
运用锁相环技术使采样频率同步跟踪信号频率，提高采样数据计算的准确性。
This paper presents a simple tracking filter circuit, which is applicable to Doppler radar sets and consists mainly of a switched bandpass filter and a phase-locked loop.
本文提出一种简单的跟踪滤波器电路，该电路可用于多普勒雷达，主要由开关式带通滤波器和锁相环组成。
Theoretical and numerical results show that the new scheme has an improved performance and remarkable complexity simplicity as compared with the classical digital delay-locked loop.
理论分析和数值结果表明，该方案较传统的延迟锁定跟踪方案明显降低了实现复杂度，而且性能有所提高。
It USES a high precision digital phase-locked loop (PLL) to accurately recover the Synchronous reference information of raw cloud-cover image data collected by the geostationary satellite.
它用高精度数字锁相环，精确地恢复地球同步气象卫星采集的原始云图数据的同步基准信息。
Phase-locked loop (PLL) has been applied in many fields.
锁相环在很多领域都得到了广泛应用。
Phase locked loop technique offers a way to resolve this problem.
锁相式频率合成技术提供了解决这一问题的思路。
A fast all digital phase-locked loop with automatic modulus control is presented.
提出了一种具有自动变模控制的快速全数字锁相环。
It also give an improved method for PLL (phase locked loop) to extract coherent carrier.
本文还对相干载波提取中的锁相环提出了一种改进方法。
The authors propose an improved phased locked loop (PLL) architecture with dual control paths.
提出一种改进的双控制通路锁相环结构。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
Now the full integrated PLL (phase locked loop) chip is used widely in radio frequency circuit.
全集成锁相环芯片目前在射频电路中应用很广泛。
This paper discusses an all digital phase-locked loop with a zero-crossing detector and a loop filter.
本文讨论的全数字锁相环包括过零检测器和环路滤波器。
The design of precise position tracking loop for DRTS with fast digital phase-locked loop is described.
本文提出一种用于光盘径向伺服系统的带有快速数字锁相环的精密位置跟踪环路的设计方案。
An automatic accurate synchronization control scheme which adopts phase locked loop principle is presented.
利用锁相环路原理提出锁相自动准同期控制方案。
In phase-coherent communication system, phase-locked loop is always used to yield coherent reference signal.
相位相干通信系统中，通常采用锁相环路来产生相干参考信号。
In this paper, a low-jitter process-independent DLL(delay locked loop) based on self-biased techniques is presented.
本文给出了一种采用自偏置技术的低抖动延迟锁相环，可应用于高频时钟产生电路。
Furthermore, the working principle and phase noise of frequency-locked loop are analyzed and discussed in this paper.
给出了实验结果，并对锁频环的工作原理、相位噪声进行了分析和讨论。
Anovel approach to implement symbol timing recovery is presented which USES a hybrid digital phase locked loop (HDPLL).
本文介绍了一种利用混合数字锁相环(HDPLL)实现码元定时恢复的新方法。
According to the theory of phase-locked loop, we use reflected photoelectric sensor to carry out the color recognition.
根据锁相环的原理，使用反射式光电传感器实现了系统的颜色识别。
The paper studies digital control scheme of resonance inverter frequency-tracking based on all digital phase-locked loop.
本文主要研究了基于全数字锁相环的谐振型逆变器频率跟踪的数字化控制方案。
Compared with traditional phase - locked loop, the design has a convenient programming and reliable operating performance.
与传统锁相环相比，该设计编程方便，工作可靠。
A novel all-digital phase locked loop (PLL), applied to the carrier synchronization of communication systems, is designed.
设计了一种用于通信系统载波同步的新数字锁相环。
The paper introduces a kind of clock recovery system based on phase-locked loop with bi-directly incident phase-comparator.
介绍了一类基于双向输入型鉴相器锁相环技术的时钟恢复系统。
The possibility of using this kind of phase-locked loop under noise interference and the problems of filter design are discussed.
文中还讨论了在噪声作用下采用这种环路的可能性和滤波器的设计问题。
We present a design for an adaptive gain phase-locked loop (PLL) that features fast acquisition, low jitter, and wide tuning range.
提出了一种快捕获，低抖动，宽调节范围的增益自适应锁相环的设计。
The industrial grating signals can be digital frequency multiplication with a phase-locked loop (PLL) controlled by a microcomputer.
用微型计算机控制锁相环(PLL)可对计量光栅信号进行数字倍频。
In this dissertation, theory, model, design and implementation of charge pump phase locked loop frequency synthesizer are lucubrated.
本文围绕电荷泵频率合成器的理论、模型、设计和实现，进行了深入的研究。
Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).
然后介绍了锁相环(PLL)的基本结构、相位模型、频率响应、噪声及杂散性能。
The software phase-locked loop (SPLL) technology in the steady speed control of permanent magnet brushless DC motor (BLDCM) in gyro was discussed.
研究了软件锁相环技术在陀螺用无位置传感器无刷直流电机稳速控制系统中的应用。
To aim at the defect of traditional sampled data acquisition scheme, a new method of realizing sampled data acquisition by phase locked loop is presented.
针对传统的取样式数据采集方案存在的缺点，提出一种利用锁相环实现取样式数据采集的新方法。
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