In the new scheme proposed, the phase lock loop is avoided and the digital logical circuit is used.
该方案利用信号自身的特性，采用数字逻辑设计，有效避免了性能不高的锁相环的使用。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
In frequency synthesis by phase lock, the loop gain will vary by the same amount due to this effect, which generally im - pedes optimization of loop performance.
在锁相频率合成器中，由于压控灵敏度的变化，环路增益也将产生同样大小的变化，这就妨碍了环路特性的最佳化。
Due to the frequency pulling of FLL, the passband of the filter in PLL can be made very narrow to suppress the noise, and the PLL can lock carrier's phase with high accuracy.
由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。
It is noted that the minimum mean square error (MMSE) detector often loses phase to lock a desired signal when the desired signal dips into a deep fade.
在实际通信系统中当信号处于深衰落时，最小均方误差(MMSE)检测器经常失去对信号的相位跟踪。
Phase lock loop and benchmark resistance compensating technologies were used to improve the detection precision, the error was less than 10%.
通过锁相放大技术及基准电阻补偿方法提高了测量的精度，误差在10%以内。
The circuits used are Chua 'circuit and phase lock loop.
所用的电路为蔡氏电路和锁相环电路。
Digital phase lock loop is a key part of the digital demodulator.
数字锁相环是数字解调器的关键部件。
The general research on the theory and technology of sampling phase lock in the paper will make a basement for the development of new product.
本论文对取样锁相理论及技术的全面研究，为新产品开发做了一定的预研工作。
This paper gives a detailed analysis of the principle of the phase lock circuit, one of the most important parts of the QF1052B Standard Signal Generator and provides some methods of checking it.
本文详细分析了QF1052B型标准信号发生器锁相环部分的基本组成及其工作原理，并提出了对此部分电路的检测方法。
This new algorithm can detect and repair cycle slips after loss of lock within 3 seconds so as to avoid the effect of cycle slips on smooth pseudo distance of carrier phase.
检验证明该方法能够准确可靠地探测并修复失锁3秒以内的周跳，避免了周跳对载波相位平滑伪距的影响。
This paper mainly discusses the design and the application of the IGBT phase lock control circuit controlled by the induction heating power supply.
本文主要介绍IGBT锁相控制电路在感应加热电源控制系统中的设计和应用。
So, after reservoir watering out as edge water and bottom water enters, the gas phase permeability will decrease greatly, and strong water lock effect will happen.
因此，当边水和底水进入储层发生水淹后，气相渗透率将极大降低，存在较强的水锁效应。
By using a double phase lock in amplifier to measure the AC strain, the measurement error can be decreased to 0.4% of the total measurement range.
如果使用双相位锁相放大器测量交变的被测量，误差将减小到全量程的0.4%以内。
The primary factor affecting fast phase lock is analyzed by using MATLAB. Then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.
应用MATLAB分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。
The conduction of special cable and special phase lock loop technology makes high signal more accurate;
特种的传导电缆和特殊的锁相环技术使高度信号更精准；
Digital phase lock loops are widely adapted in nowadays communication systems. However, it is difficult to design the loop parameter precisely.
数字锁相环在实际通信系统中应用广泛，但其精确的环路参数设计比较困难。
The task of a phase-lock receiver is to reproduce the original signal while removing as much of the noise as possible.
锁相接收机的作用是重建原信号而尽可能地去除噪声。
How to raise the phase lock speed of embedded DPLL is researched.
对如何提高嵌入式全数字锁相环的锁定速度进行了研究。
Phase lock oscillator, address coding and intermission mode are taken to stabilize the system and to promise the targets working period longer than 10 day.
系统中采用了锁相技术和地址编码，并采用间隙工作方式，使得本系统工作性能稳定，目标源一次充电可连续工作10天以上。
A systematical analysis of dynamic characteristic of the pulse-synchronous camera control ystem is described, as to make the results help the researches in phase lock speed-stabilizing ystem.
本文对脉冲同步摄影机控制系统的动态特性进行了系统的分析，以便使所得结果对锁相稳速系统等方面的研究有所帮助。
A fast phase-lock feature can also be enabled to give switch times between 11 and 22 ms depending on absolute frequency and step size.
一种快速锁相功能，也可以启用，使11日至22日开关时间取决于绝对频率和步长毫秒。
The phase- locked loop is one kind of control system which is able to achieve phase automatic lock, to compose frequency and to trace demodulation system.
锁相环路是一种能实现相位自动锁定的控制系统，主要用于频率合成及跟踪解调系统。
Finally, a simulation analysis for the improved FFT frequency correction technology and phase-lock loop is maked, the result shows that the method also has a good performance in the low SNR situation.
最后分别对改进的FFT校频技术及锁相环进行了仿真分析，结果表明该方法在低信噪比下仍具有良好的性能。
The synchronization and separation of the data and clock from floppy disk driver are one of phase-lock techniques' use in computer field.
对软磁盘的数据和时钟的同步和分离，只是锁相技术在计算机领域的应用之一。
The simplified method has been adopted to confirm the limit frequency of limit circle of phase-lock control loop. The general expression of the capture band has been derived.
采用简化的方法确定锁相回路的极限环频率极限，推导出捕捉带的一般表达式；
This study aims at investigating the lock-in phenomenon, fluctuating lift and the phase shift between fluctuating lift and displacement of the oscillating cylinder.
文章重点研究了较高振幅振动柱的锁定现象、波动升力与柱位移之间的相位变化，讨论了方柱涡激振荡、驰振和气动稳定性问题。
Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals.
低阶锁相环跟踪频率斜升信号时产生的稳态相差致使环路失锁，接收机无法锁定载波信号。
The orthogonal analog phase lock loop is used to get the timing information of the impulse radio system and the multi-path component separation.
使用正交模拟锁相环路对无载波的脉冲无线电系统实现多径捕获和同步提取。
The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.
数字锁相环路（DPLL）是数字相干解调技术的核心。
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