The digital lock-in technique is used to rather extract the effective signal from the noise and reduce the measurement error.
采用数字锁相技术从噪声中提取有效信号，以减小测量误差。
By using a double phase lock in amplifier to measure the AC strain, the measurement error can be decreased to 0.4% of the total measurement range.
如果使用双相位锁相放大器测量交变的被测量，误差将减小到全量程的0.4%以内。
Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals.
低阶锁相环跟踪频率斜升信号时产生的稳态相差致使环路失锁，接收机无法锁定载波信号。
Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals.
低阶锁相环跟踪频率斜升信号时产生的稳态相差致使环路失锁，接收机无法锁定载波信号。
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