To improve the fault coverage, storage-mode is added to LFSR-mode.
用随机测试模式加存储测试模式，来提高故障覆盖率。
A new BIST structure with the method of test vector generation based on a controlled LFSR is proposed.
本文提出了一种基于受控线性反馈移位寄存器（LFSR）进行内建自测试的结构及其测试矢量生成方法。
Results from initial experiments show that an 8 ~ 24 degree LFSR can be formed by linking 1 ~ 7 degree LFSR's.
初步的实验结果表明，从8至24级的线性反馈移位寄存器都可以由1至7级的线性反馈移位寄存器链接构成。
Constrained input reduction, LFSR coding and folding counter are applied to compress and generate a deterministic test set.
运用有约束的输入精简、LFSR编码与折叠计数器技术，实现了对确定性测试集的压缩与生成。
Controllable LFSR can adjust test vector sequence generated by original LFSR through control codes which stored in the ate or ROM.
可控LFSR可以通过一些控制码对LFSR的原始产生顺序进行调整，这些控制码存储在ate中或ROM中。
For low power consumption during test mode, the proposed approach ignores the non detecting vectors by altering the structure of LFSR.
通过改变线性反馈移位寄存器的结构滤掉无效的测试矢量从而实现低功耗测试。
Generalized self -shrinking sequences is a class of sequence, which is based on LFSR, with irregularly clocked, and it has good pseudo-randomness.
广义自缩序列是基于LFSR的一类非常规钟控的序列，具有良好的伪随机性，可以用作加密时的密钥流。
In this paper, a scheme is presented, in which an infinite length's LFSR with non maximum cycle sequence is used as a built-in test generator in digital systems.
本文介绍了一种使用非最长周期序列的非定长线性反馈移位寄存器作为数字系统内部测试生成器的方案，并给出了设计这种测试生成器的设计过程和算法。
The test vectors of some sub-scan chains generate by controllable LFSR when these chains only need to update test vector and do not need to shift out test responses.
当某个子扫描链的测试向量需要更新且又不需要移出其测试响应时，其测试向量由可控LFSR产生。
For all benchmark circuits, the method is able to encode all deterministic test patterns using an LFSR whose size is equal to the maximum number of care bits in a test pattern.
对于所有的实验电路，通过使用级数为确定性测试向量的确定位数量最大值的线性反馈移位寄存器，本策略可以编码所有的确定性测试向量。
A traditional linear feedback successive-displacement register (LFSR) random sequence has recurrence character generally, so it makes the ability of anti-attacking of encrypted files poor.
传统的线性移位寄存器序列具有递推性，导致密文抗攻击能力不强。
CRC computing by software can hardly meet with the high speed digital system. Classic LFSR circuit and other algorithm that derived from software are generally adopting as hardware solutions.
用软件实现CRC校验码计算很难满足高速数据通信的要求，基于硬件的实现方法中，有串行经典算法LFSR电路以及由软件算法推导出来的其它各种并行计算方法。
CRC computing by software can hardly meet with the high speed digital system. Classic LFSR circuit and other algorithm that derived from software are generally adopting as hardware solutions.
用软件实现CRC校验码计算很难满足高速数据通信的要求，基于硬件的实现方法中，有串行经典算法LFSR电路以及由软件算法推导出来的其它各种并行计算方法。
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