An efficient network comparison algorithm for layout verification of integrated circuits is presented.
提出了一种有效的验证集成电路版图的网络比较算法。
The basic theory of resistance extraction in VLSI layout verification is described. A novel resistance extractor based on the boundary element method is presented.
介绍了VLSI版图验证中电阻提取的基本原理和主要方法，给出了一种新颖的基于边界元法的电阻提取算法。
The basic theory of resistance extraction in VLSI layout verification is described. A novel resistance extractor based on the boundary element method is presented.
介绍了VLSI版图验证中电阻提取的基本原理和主要方法，给出了一种新颖的基于边界元法的电阻提取算法。
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