This allows more latency hiding and less instruction pipeline stalls, and the code runs faster as a result.
这将允许更多的延迟隐藏和更少的指令管道摊位,和代码运行更快。
Software pipelining has been combined with several memory optimization technologies for higher performance by hiding memory access latency.
为了减轻存储系统影响,软件流水结合了一些存储优化技术,通过隐藏存储延迟来提高性能。
This paper proposed a packet processing engine architecture called NRS05, that promotes the efficient dynamic thread scheduling for hiding long latency operations and coping with pipeline stalls.
本文介绍了一个专门面向网络协议处理的硬件多线程包处理微引擎NRS05的设计。
This paper proposed a packet processing engine architecture called NRS05, that promotes the efficient dynamic thread scheduling for hiding long latency operations and coping with pipeline stalls.
本文介绍了一个专门面向网络协议处理的硬件多线程包处理微引擎NRS05的设计。
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