Execute a Return from Interrupt instruction;
执行中断返回指令；
The interrupt instruction passes control to a kernel handler, which after executing a replacement function, returns to continue executing the process.
中断指令将控制传递给内核句柄，后者在执行替换函数执行之后，返回来继续执行该进程。
An instruction storage interrupt is a page fault on an instruction fetch.
指令存储中断通常是指在取出指令时发生页面错误。
"And hand you the phone if the call is for you, to not interrupt or make noise when you are talking on the phone (this will take many months of instruction), and to not bang down the receiver."
在你谈电话时不要打断或制造噪音(这会耗费很多时间去教导的)；并且不要“啪”一声重重地挂电话。
400-instruction Storage Interrupt (ISI).
400-指令存储中断(ISI)。
You set some registers and issue a system call instruction (or an interrupt) and have the kernel code called directly from the trap handler.
你可以设置一些寄存器，并发出一个系统调用指令(或中断)，并由陷阱处理程序直接调用内核代码。
While it is running, it records the address of the instruction that is being executed every time a system-clock interrupt occurs.
当它运行时，它会记录每次系统时钟中断发生时正在执行的指令的地址。
In other words, the instruction processed by the control unit after dealing with the interrupt signal is the first instruction of the selected handler.
换句话说，控制单元在解决完中断信号后，处理的指令就是选中的处理函数的第一条指令。
Before dealing with that instruction, the control unit checks whether an interrupt or an exception occurred while the control unit executed the previous instruction.
在执行这个指令之前，控制单元检查在它执行前一条指令时，是否有中断或异常产生。
This paper analyses the return instruction of MCS-51 and gives the answer to releasing the interrupt. Some special use and program are also given.
分析了MCS一51单片机返回指令，解决了如何释放中断逻辑的问题，并给出一些特殊用法及实用程序。
These values define the logical address of the first instruction of the interrupt or exception handler.
这些值定义了中断或异常处理函数的第一条指令的逻辑地址。
Chapter 3 is devoted to the analysis of the kernel structure of DSP56F807, and the introduction of the instruction system and the interrupt mechanism.
第三章对DSP56F807的内核结构进行了分析，并介绍其指令系统和中断机制。
Basically, a feature of the CPU that permits the machine to mask an interrupt request until the following instruction has been completed.
中央处理机的一种基本特性，在下一条指令执行完毕前允许屏蔽中断请求。
Basically, a feature of the CPU that permits the machine to mask an interrupt request until the following instruction has been completed.
中央处理机的一种基本特性，在下一条指令执行完毕前允许屏蔽中断请求。
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