You should prefer using this interface to trying to write your own, and you should definitely stay away from writing your own timer code in an environment like the N810.
您应该喜欢使用这种接口尝试编写自己的警报，而且您肯定不会在 N810这类环境中编写自己的计时器代码。
The programmatic interface of this class is not consistent with the other two timer classes and it's also a bit more cumbersome.
这个类的可编程接口同其它两个类也不一致，它稍微有点麻烦。
As with the Work interface, this class extends Runnable, and Timer invokes the run method at the appropriate times.
同使用Work接口时一样，这个类扩展了Runnable，而且Timer会在适当的时间调用run方法。
Because Timer is a class rather than an interface and the threads are actually spun off in that class's constructors, an application server cannot modify this behavior.
因为Timer是类而不是接口，而且线程实际是在类的构造函数中产生的，所以应用服务器不能修改这种行为。
This scheme is applied to the human interface of computer knitting machine, basically benefiting from the strong function of STM32... DMA transmission and advanced application of the timer.
本方案能成功应用在电脑横机的人际界面显示中，主要得益于STM 32的强大功能：DMA传输以及高级定时器等的应用。
In an uniformly accelerated motion experiment, the moment of a cart passing through the measuring point is recorded by PC's serial interface instead of pointing timer.
在匀变速直线运动的实验中，利用PC机的串行接口来记录运动小车通过测量点的时刻值，以此代替打点计时器计时。
This paper introduces a hot switchover apparatus with main computer and multi-channel transmission system, which comprises IEEE-488 interface and monitoring timer.
本文介绍利用IEEE- 488接口和监视定时器组成的主计算机与多路通讯管理机通讯系统的实时双机热切换装置。
This paper proposes a method of intelligent time-control switch design, which USES the SCM timer, IO interface, interrupt system, and other resources to control the multi-channel switch.
本文提出了一种智能时控开关的设计方法，该智能时控开关利用单片机中的定时器、IO接口、中断系统等资源，能根据时刻信息对多路开关进行控制。
In this paper, the optimization method was used to design the interface circuit, and use VHDL description to design low voltage digital delay timer.
在电路设计过程中，对后级接口电路进行了最优化设计，采用VHDL描述的方式实现了低压数字延时电路模块的设计。
In this paper, the optimization method was used to design the interface circuit, and use VHDL description to design low voltage digital delay timer.
在电路设计过程中，对后级接口电路进行了最优化设计，采用VHDL描述的方式实现了低压数字延时电路模块的设计。
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