That defines an interface with a method for writing a buffer of bytes.
这里定义了一个接口和一个写字节缓冲的方法。
A message passing interface (MPI) manages this buffer.
消息传递接口(MPI)管理此缓冲区。
To benefit from the solution, you must clearly define a lasting concrete abstract data buffer interface.
为了从这种解决方案中获益，您必须清楚地定义具体的抽象数据缓冲区接口。
Considering all that, a properly designed data buffer interface is required!
考虑到所有这一切，设计一个适当的数据缓冲区接口就势在必行！
Sbappend adds the data at the end of send buffer and tcp_output sends the segment onto the interface.
sbappend在发送缓冲区的末尾添加数据，并且tcp _ out put将该段发送到接口。
Repeated opening and closing of Ambulant from the command-line interface (CLI) destroys the error buffer each time.
通过命令行界面(CLI)重复打开和关闭ambulant每次会破坏错误缓冲。
Below the buffer cache are the device drivers, which implement the interface for the particular physical device.
缓冲区缓存之下是设备驱动程序，它实现了特定物理设备的接口。
Its programming interface is based on message, which makes it convenient to buffer management, flow control, and priority based message schedule strategy.
它的编程接口是基于消息的，使得缓冲区管理，流量控制，和按优先级传送消息都很易于实现。
The method to implement data buffer and logical control of the data transfer through FPGA was introduced, and the design of the interface between FPGA and AD9240 was also shown up.
对如何用FPGA实现该数据采集系统的数据缓存和数据传输的逻辑控制，以及FPGA与AD9240的接口设计等给出了详细说明。
The interface uses a circuit based on dual port FIFO buffer memory to realize data transfer of different I/O velocity between the two computers.
该接口采用双端口FIFO缓冲存储技术，实现两机间不同I／O速度的数据通信。
Each processing module may include a network interface, at least one buffer, a packet parser, a packet builder, and at least one processing unit.
每一个处理模块都可以包括网络接口、至少一个缓冲器、分组解析器、分组构造器和至少一个处理单元。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
Secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc.
详细叙述了通讯板接口模块的硬件结构设计，其中，对数据缓冲电路、数据传输速率选择电路、逻辑控制电路等各关键点做了重点介绍；
The SDRAM has become the chief choice of the buffer storage because of its high speed, great capacity, and low price; but due to its complex control timing, it cannot directly interface with DSP.
同步动态随机存储器（SDRAM）具有高速，大容量，价格低廉等优点，因而成为缓冲存储器的首选，但是SDRAM控制时序比较复杂，不能与DSP直接接口，这极大地限制了它的广泛应用。
The FPGA is designed as a MVB controller which consists of Manchester encoder, Manchester decoder, buffer, center control unit, internal memory, MCU interface and so on.
FPGA实现MV B控制器功能，分为曼彻斯特编码器、解码器、缓冲区、中央控制单元、内部存储器和单片机接口等几部分。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
Transfer device at interface points can be turntables or lift tables. Auxiliary devices of the system include turntable at work station, pallets, stopping device and buffer on stopping device.
衔接输送设备的转换机构有回转台式和升降式转换机，系统的附属装置包括有工位上的回转台、托盘与各工位的停止器以及停止器上的缓冲器等。
Transfer device at interface points can be turntables or lift tables. Auxiliary devices of the system include turntable at work station, pallets, stopping device and buffer on stopping device.
衔接输送设备的转换机构有回转台式和升降式转换机，系统的附属装置包括有工位上的回转台、托盘与各工位的停止器以及停止器上的缓冲器等。
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