This paper introduces the problems of Signal Integrity in high-speed parallel bus interconnect design and the new design methodology.

本文介绍了高速并行总线互连设计中出现的信号完整性问题及新的设计方法学。

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In Chapter 2, the analysis methods concerned with high speed interconnect design are discussed, including the formulation of circuit equations and model reduction algorithm.

第二章论述了现今高速互连设计使用到的分析方法，包括电路方程的表述和模型简化算法。

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In this thesis, the interconnect model in the SOC design, and the delay, power and design method for layout design are investigated from the perspective of interconnect design.

本文主要针对SOC中的连线模型以及从连线设计角度对版图设计中的时延、功耗以及设计方法进行研究。

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In this thesis, the interconnect model in the SOC design, and the delay, power and design method for layout design are investigated from the perspective of interconnect design.

本文主要针对SOC中的连线模型以及从连线设计角度对版图设计中的时延、功耗以及设计方法进行研究。

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