This method can be applied to the built in self test of equipment and accomplish on line fault detection of period signals.
该方法可应用到设备内部自测试中，并可完成周期信号的在线故障检测。
Built in self test, diagnostic procedures, error automatically prompts and can automatically measure and display the ambient interference.
〇内置自我诊断程序，开机自检，出错自动提示并能够自动测量和显示周围环境的干扰情况。
Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.
另外，本文还针对IP核投片测试提出一种扫描测试电路结构，能够实现测试芯片的扫描测试和高速内建自测试(BIST)。
Aiming at the mixed-signal circuit testing, an integrated built-in self test (BIST) architecture for testing on-chip high speed ADC was presented.
针对混合信号电路的测试问题，提出了一种内建自测试(BIST)结构，分析并给出了如何利用该结构来计算片上高速模数转换器(adc)的静态参数。
Built-In self test: An electrical testing method that allows the tested devices to test itself with specific added-on hardware.
嵌入式自测试：一种在特别添加的硬件中允许被测元件自我测试的电子测试方法。
For the test and verification of soft-IP, the paper presents a solution of Design For test technique, of which the BIST (Built-in Self test) is described in particular.
针对IP软核的测试、验证提出了面向测试、验证的IP软核设计方法—BIST内建自测试方法。
Built-in self-test (BIST) is used as an effective test technique and it can greatly reduce test overheads.
内建自测试(BIST)作为一种有效的测试技术可以大大地降低测试开销。
To reduce the storage volume of the test data during the built-in self-test (BIST), a new BIST technique based on two dimensional compression of test data is presented.
为压缩内建自测试(BIST)期间所需测试数据存储容量，提出了一种新的基于测试数据两维压缩的BIST方案。
Based on the research of primary DFT method and the structure characteristic of designed CPU, the article combines the boundary scan and Build-In Self-Test based on BILBO to test.
本文在对目前主要的可测性设计方法进行研究的基础上，根据所设计CPU的结构特点，采用了边界扫描技术和基于BILBO的内建自测试技术结合的可测性设计方案。
A low power test approach for test or built-in self-test based on arithmetic additive generator is proposed in this paper.
本文提出了一种基于算术加法生成器的测试或内建自测试的低功耗测试方法。
The principle of memory built-in self-test is analyzed in detail and a typical implementation of MBIST is given in the paper.
文中详细分析了嵌入式存储器内建自测试的实现原理，并给出了存储器内建自测试的一种典型实现。
As a new method of design for testability build-in self-test can prominently improve the testability of the circuits.
内建自测试作为一种新的可测性设计方法，能显著提高电路的可测性。
Reseeding is a built-in self-test (B. IST) testing method, which is used to improve fault coverage of pseudo-random testing.
重新播种的测试方法是一种内建自测试方法，它可以用来提高伪随机测试矢量的故障覆盖率。
This paper presents a new structure of analog Built - in Self - Test circuit (ABIST) consisting of analog multiplexers.
本文提出了采用模拟多路开关的模拟内建自测试电路abist的一种新结构。
This paper presents a new structure of analog Built - in Self - Test circuit (ABIST) consisting of analog multiplexers.
本文提出了采用模拟多路开关的模拟内建自测试电路abist的一种新结构。
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