A fast access time is obtained by utilizing a bit line equalizing technique, a high speed hierarchical sense amplifier and a preset data output buffer.
采用位线平衡技术、高速两级敏感放大器及可预置电压的数据输出缓冲，以提高存储器的读写频率。
A high speed data collector and buffer, applied to detect weak signal in strong noise, is described in the paper.
本文介绍一种在强噪声下弱信号检测中的高速数据采集缓冲系统。
Based on a method of 2 dimension data rearrange, a high speed and high efficiency implementation of DRAM access is proposed in the design of block buffer manager.
在数据块缓冲管理器的设计中，采用一种基于二维数据重排的访问方式，实现高速高效的DRAM访问。
Based on a method of 2 dimension data rearrange, a high speed and high efficiency implementation of DRAM access is proposed in the design of block buffer manager.
在数据块缓冲管理器的设计中，采用一种基于二维数据重排的访问方式，实现高速高效的DRAM访问。
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