The paper presents a square wave modulation scheme based on TDMA signal system to resolve the problem. Also it can avoid the high speed system clock.
该文提出了一种基于TDMA信号体制下的方波调制方案，该方案既解决了远近效应，又避免了在较高的中频上采用过高的系统时钟。
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
The system based on the frequency synthesizer can offer a high accuracy, high stability and low jitter clock for a high speed and high precision backplane test platform.
该时钟板基于频率合成器来产生高精度、高稳定度、低抖动的时钟，用于高速高精度背板测试平台。
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
In the Red Bull Air Race World Championship, you play the role of one of the world's best pilots navigating aerial tracks and flying between Air Gates - all in a high speed race against the clock.
在本游戏中，玩家将驾驶特技飞机参加红牛杯世界飞行特技锦标赛。你需要按照画面上的提示路线进行飞行，同时你还要保持飞行的速度，不然超时的话就失去了夺冠的机会了。
The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
该系统采用了片同步技术实现了采样后高速数字信号的可靠锁存，采用高精度的时钟管理芯片和设计合理的时钟路径对时钟抖动做了严格控制。
It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port.
它内置一个低功耗、高速、16位不失码的采样adc、一个内部转换时钟和一个多功能串行接口。
Because of the limits of feedback devices, high speed pseudo noise code generation cannot depend simply on the improvement of clock rate.
由于反馈器件的限制，高速伪码不能采用单独依赖提高时钟频率的方法。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
Phase matching is of particular concern with some high speed digital circuits, because unmatched cables may cause excessive clock skew, resulting in erroneous operation.
由于不匹配的电缆可引起过度的时钟相偏（Clock Skew），导致错误操作，所以相位匹配是有些高速数字电路中特别要注意的事项。
The low power consumption digital true random source comprises a high speed random oscillator signal generator, an alternative oscillation stop control unit, a clock generator and a sampling unit.
它包括高速随机振荡信号发生器、交错停振控制单元、时钟发生器和采样单元。
A kind of GPS satellite synchronous clock based on the DS80C320 High-speed SCM is recommended in the following thesis, to solve problem mentioned above.
针对这种情况，本文设计了一种基于DS80C 320高速单片机的GPS卫星同步时钟。
A kind of GPS satellite synchronous clock based on the DS80C320 High-speed SCM is recommended in the following thesis, to solve problem mentioned above.
针对这种情况，本文设计了一种基于DS80C 320高速单片机的GPS卫星同步时钟。
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