高速缓冲器HSB ？
OPS still is placed in to study the stage because of lacking of the high-speed optical logic device and optical buffer.
光分组交换由于缺乏高速光逻辑器件、光缓冲存储器等，因此还处于研究阶段。
Without opening mould, it can provide accurate buffer, high speed gap filling and high strength of supporting and positioning for different volume, switch and weight products.
无需开模，即可为不同体积、开关和重量的产品，提供精确的缓冲、高速空隙填充或者高强度的支撑定位。
A fast access time is obtained by utilizing a bit line equalizing technique, a high speed hierarchical sense amplifier and a preset data output buffer.
采用位线平衡技术、高速两级敏感放大器及可预置电压的数据输出缓冲，以提高存储器的读写频率。
A high speed data collector and buffer, applied to detect weak signal in strong noise, is described in the paper.
本文介绍一种在强噪声下弱信号检测中的高速数据采集缓冲系统。
Making use of large inner capacity and programmable resource of a CPLD chip, a high speed UART with buffer bas been designed to meet communication requirement.
利用CPLD芯片的大容量、可编程特性，设计了具有缓存功能的高速异步串行通信接口芯片，以满足日益提高的快速串行通信要求。
The SDRAM has become the chief choice of the buffer storage because of its high speed, great capacity, and low price; but due to its complex control timing, it cannot directly interface with DSP.
同步动态随机存储器（SDRAM）具有高速，大容量，价格低廉等优点，因而成为缓冲存储器的首选，但是SDRAM控制时序比较复杂，不能与DSP直接接口，这极大地限制了它的广泛应用。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
Description: 1, exquisite appearance. 2, passenger comfort, quality of light, 3, high-speed performance, anti-skidding good performance. 4, rolling resistance small buffer good performance.
产品编号：轻型轮胎 产品简介：1、外观精美。2、乘用舒适，质优量轻，3、高速性能好，防侧滑性能好。4、滚动阻力小，缓冲性能好。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
The output buffer has ability of switching the output voltage to be low level and high level in high-speed.
此输出缓冲器可快速地将输出电压切换为低电平和高电平。
Based on a method of 2 dimension data rearrange, a high speed and high efficiency implementation of DRAM access is proposed in the design of block buffer manager.
在数据块缓冲管理器的设计中，采用一种基于二维数据重排的访问方式，实现高速高效的DRAM访问。
高速缓冲器寄存器HSBR ？
高速缓冲器寄存器HSBR ？
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