The proposed method can generate simplified test patterns with high fault coverage, and can detect multiple faults as many as possible.
新方法可生成精简的、故障覆盖率高的测试图形，并尽可能多地检测多重故障。
Experimental results show that the proposed testing algorithms have merits such as high fault coverage, strong diagnostic ability and less testing time.
实验结果表明，此测试算法具有故障覆盖率高，诊断故障能力强，测试需要的时间少等优点。
This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented fort…
本文论述了板级边界扫描测试存取口的故障模型和测试原理，并针对全边界扫描印制板提出了一种故障覆盖率高、测试时间短的测试算法。
For testing chip pins, the fault coverage can reach 100%, and the fault position can be positioned with high accuracy.
对芯片管脚的测试可以提供100%的故障覆盖率，且能实现高精度的故障定位。
This paper presents an approach to delay testing with duplicating variable observation points, which provides a high path delay fault coverage by testing a small number of paths.
本文提供了一种使用双倍可变观测点进行时滞测试的方法，保证了只需要测试少量通路就能完成整个电路的时滞测试。
This paper presents an approach to delay testing with duplicating variable observation points, which provides a high path delay fault coverage by testing a small number of paths.
本文提供了一种使用双倍可变观测点进行时滞测试的方法，保证了只需要测试少量通路就能完成整个电路的时滞测试。
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