This is achieved through pipelining at the hardware level.
在硬件级别中，通过使用流水线操作来完成这个任务。
To overcome the shortcoming of low speed and low efficiency of genetic algorithm's software implementation, two hardware implementation schemes of serial and pipelining realization are put forward.
针对遗传算法软件实现速度慢、效率低的缺点，提出了便于算法实现的串行和流水线两种硬件实现方案。
A new method for calculating 2-d mask convolution based on FPGA is presented. Compared with traditional methods, it achieves the same depth of pipelining with fewer hardware resources.
本文提出了一种基于FPGA的模板卷积运算的新方案，相比传统方案，这种方案在结构上能以较少的硬件资源达到相同的流水深度。
To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。
To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。
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