The harmonic analysis with the FFT processing nucleus based on the internal hardware multiplier is analyzed in detail.
给出了系统硬件结构，对以内部硬件乘法器为FFT处理核的谐波分析技术进行了详细分析。
DSP adopts Harvard structure in which program memory and data memory are divided. DSP can realize various digital signal process algorithms by special hardware multiplier.
DSP内部采用程序和数据分开的哈佛结构，具有专门的硬件乘法器，可以用来快速地实现各种数字信号处理算法。
The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
说明了对偶基比特并行乘法器在硬件规模上的优越性。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The disclosed multiplier block has a processing speed higher than conventional multipliers and requires minimal extra cost for the hardware needed for re-configuration.
扩程逻辑块的处理速度比传统的扩程器都要快，而且需要重新配置的硬件额外成本要求最低。
The disclosed multiplier block has a processing speed higher than conventional multipliers and requires minimal extra cost for the hardware needed for re-configuration.
扩程逻辑块的处理速度比传统的扩程器都要快，而且需要重新配置的硬件额外成本要求最低。
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