Addend and the summand input, and digital and carry the output device is a half adder.
加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。
A real time optical logic processor is presented, that can perform binary logic operations in parallel. Experimental result is given of the system as a half adder.
本文提出了一种能实时完成二进制逻辑运算的光学并行处理系统，并给出了作为半加法器的实验结果。
It is called "half-adder" because it has only two inputs and does not provide for a carry input.
它之所以称为半加器是因为它只有两个输入，即没有进位输入。
This paper brings forward a new viewpoint of using balanced ternary half-adder in the ternary optical computer.
提出了在三值光计算机中采用对称三进制半加器的观点，设计了支持这个观点的半加器结构原理图。
Non coherent demodulation for 2PSK detects relation of carrier wave phase of the interval symbol by the (half period of carrier wave) delay and the adder, then the data is demodulated.
PSK非相干解调法将经延时半个载波周期的接收信号与原接收信号相加，检测出两相邻码元载波相位变化情况，从而解调出数字信息。
Non coherent demodulation for 2PSK detects relation of carrier wave phase of the interval symbol by the (half period of carrier wave) delay and the adder, then the data is demodulated.
PSK非相干解调法将经延时半个载波周期的接收信号与原接收信号相加，检测出两相邻码元载波相位变化情况，从而解调出数字信息。
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