This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.
这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
This paper concentrates on using gated-clock in low-power design of CMOS circuits.
阐述了如何运用门控时钟来进行CMOS电路的低功耗设计。
This paper concentrates on using gated-clock in low-power design of CMOS circuits.
阐述了如何运用门控时钟来进行CMOS电路的低功耗设计。
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