Features: Low power gate trigger circuits.

特点：低功率控制极电路。

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A pulse to gate the output of a core memory sense amplifier into a trigger in a register.

将磁心存储器读出放大器的输出选通到寄存器的触发器中的一种脉冲。

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Through redesigning the structure of the original PFD circuit and based on the traditional D trigger PFD, two new PFDs, transmission gate D trigger PFD and flip-latch based PFD were proposed.

通过对原有PFD电路结构进行重新设计，在传统D触发器PFD的基础上提出了两种新型PFD：传输门D触发器型PFD和基于锁存器的PFD。

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The digital trigger to silicon controlled rectifier based on field programmable gate array (FPGA) has high accuracy and the ability of phase self-adjusting.

以现场可编程门阵列（FPGA）作为触发脉冲生成器，精确性高，并具有相序自适应性。

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When the voltage applied to anode again becomes positive the gate will trigger the SCR on again.

当施加到阳极的电压再次变为正的栅极将再次触发可控硅上。

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The end player forms the anode, and the end n-layer is the cathode, while the player adjacent to the cathode forms the gate or trigger electrode.

端头的p层形成阳极，端头的n层是阴极，而与阴极相邻的p层形成门极（即触发极）。

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The end player forms the anode, and the end n-layer is the cathode, while the player adjacent to the cathode forms the gate or trigger electrode.

端头的p层形成阳极，端头的n层是阴极，而与阴极相邻的p层形成门极（即触发极）。

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