Using gate level modeling might not be a good idea for any level of logic design.
使用门级建模对于任何逻辑设计都不是一个好的设计。
The energy optimization methods in circuit level and gate level have been investigated widely.
线路层、门层等低层能量优化方法已经得到广泛研究。
Constant components and output opened ports in the result of high level synthesis lead to explicit redundancy in gate level technology mapping.
高级综合结果中常量元件和输出悬空端口导致门级工艺映射结果中存在显式冗余。
This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.
这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
The traditional magnitude comparator is based on gate-level techniques and not suitable for VLSI design.
传统的数字比较器采用门级设计技术，电路结构不规则，不利于大规模集成电路的设计。
The traditional magnitude comparator is based on gate-level techniques and not suitable for VLSI design.
传统的数字比较器采用门级设计技术，电路结构不规则，不利于大规模集成电路的设计。
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