The design and successful results of the range gate circuits have been given.
提供了距离门设计方案和应用结果。
The alternating-complementary locator is constructed by D-flip-flops and gate circuits. It is proved that it is totally fault locating.
交替互补定位器由D型触发器和通用门电路构成，它被证明为是一个完全故障定位的定位器。
The XOR map is presented that is a graphic for design base on exclusive-OR gate circuits and is follow the example of the Karnaugh map.
仿效卡诺图设计了以异或门为基本电路的电路设计用图—异或图。
Digital logic gate circuits are manufactured as integrated circuits: all the constituent transistors and resistors built on a single piece of semiconductor material.
数字逻辑门电路作为集成电路被制造：所有组成的晶体管和电阻建立在一块半导体材料上。
This paper presents two CMOS practical circuits for the optimal Universal-Logic-Gate (ULG. 2).
本文提出了最佳通用逻辑门ulg。2的两种CMOS实用电路。
Due to the subtle error among different manufacturing equipment, the gate delay of circuits is different and varies in a given scope, which induces the time uncertainty of the waveform.
由于制造设备本身存在微小误差，具体门的延时并不相同，而是在一定范围内变化，引起波形变化的时间不确定。
Based on the working principle, counter structure and Clocked Transmission Gate Adiabatic Logic circuits, a design scheme of decimal counter with reset is proposed.
通过对计数器和钟控传输门绝热逻辑电路工作原理及结构的研究，提出一种带复位功能的低功耗十进制计数器设计方案。
An assistant 380V AC-input and multi-output switching power supply is introduced which is used in thick-film driving circuits for large-power IGBT(Insulated Gate Bipolar Transistor).
介绍了一种用于大功率IGBT厚膜驱动电路的380V系统输入、多路输出辅助开关电源。
The approach can be easily incorporated into existing RTL to gate equivalence checking frameworks and increase the robustness of equivalence checking for arithmetic circuits.
本算法可直接结合到现有的RTL和门级网表的验证流程中，从而提高算术电路的验证能力。
The reliability of super thin gate oxides is bne of the most important problems in MOS integrated circuits.
超薄栅氧化层的可靠性是MOS集成电路中最重要的问题之一。
Over-current protection circuits convert the detecting current into the gate voltage which controls the switch FET.
过流保护电路将检测电流转化为栅压控制开关管；
In chapter 5, the on-screen driving circuits composed of P-channel TFT have been designed, including inverter, shift register, transmission gate and simulated using simulation software.
第五章设计了全p沟道tft构成的屏上驱动电路，包括反相器、移位寄存器、传输门的设计，并用仿真软件进行了仿真验证。
As a result of the simplification, we can now build much simpler logic circuits performing the same function, in either gate or relay form.
用简化后的结果，我们现在建立简单的逻辑电路来实现相同的功能，用其它门或设备组成。
A field programmable gate array relates to the technology of integrated circuits.
现场可编程门阵列，涉及集成电路技术。
Features: Low power gate trigger circuits.
特点：低功率控制极电路。
The paper also discusses the design principle of super-high-speed digital circuits and some examples of combinational and sequential circuits using linear AND-OR gate are given.
本文还讨论了应用线性“与或”门设计超高速数字电路的准则以及有关的组合和时序电路设计实例。
The ECL OR-AND-gate can simplify a generalized ECL circuits structures, for example, an ECL double-edge-triggered D flip-flop.
作为常规ECL门的补充类型，常可用于简化一般ECL电路结构，例如ECL双边沿D触发器。
QBTL is designed specially for use as a four-valued threshold gate with which varied four-valued composite logic circuits can be formed.
其中QBTL设计成可单独作为四值“阀”门使用，用于构成其他四值组合逻辑。
In this circuits microwave crystal detectors is adopted for the sampling gate.
设备采用了普通的漂移晶体管和微波晶体检波器。
In this paper, a 10k-gate radiation tolerant CMOS gate array has been developed to assess the intrinsic radiation hardness of circuits built at standard commercial CMOS foundries.
本文利用标准的商业CMOS工艺，设计了一个1万门的抗辐射加固的CMOS门阵列，用以评估商业工艺线制造的电路的抗辐射水平。
Then the all basic-circuits are also designed and simulated carefully including active resister, current mirrors, comparator, inverter, AND gate, OR gate.
其次对集成电路内所需要的基本模拟及数字电路如有源电阻、电流镜、电压比较器、与门及或门进行了设计和仿真。
This kind of gate circuit can be used in forming 4 value combination logic circuit and order part logic circuit, it also can be combined with DYL series circuits.
这类门电路可以用于构成四值组合逻辑电路和时序逻辑电路，也可以和DYL系列电路配合使用。
This kind of gate circuit can be used in forming 4 value combination logic circuit and order part logic circuit, it also can be combined with DYL series circuits.
这类门电路可以用于构成四值组合逻辑电路和时序逻辑电路，也可以和DYL系列电路配合使用。
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