As an example, a clustering algorithm is given for gate arrays with macrocells to obtain multi-objective optimization.
作为例子，针对带宏单元的门阵列给出了相应的算法。
In this dissertation, Field Programmable Gate Arrays (FPGA) chip is studied to develop and design the fine interpolation chip.
本文着重研究用现场可编程门阵列(FPGA)来开发设计精插补芯片。
As a major new feature, the system is developed for a reconfigurable platform based on Field Programmable Gate Arrays (FPGAs).
作为一个重要的新功能，该系统可重构开发平台，基于现场可编程门阵列(FPGA)。
A digital hardware control scheme of shunt active power filter (SAPF) based on field programmable gate arrays (FPGA) is introduced.
提出一种基于现场可编程门阵列(FPGA)的并联型有源电力滤波器(SAPF)的控制器方案。
On this basis, a prototype is developed with a high speed digital signal processor (DSP), huge field-programmable gate arrays (FPGAs) and real-time software.
在此基础上，采用高速数字信号处理器（DSP）、大规模现场可编程门阵列（FPGA）和实时软件进行系统设计，完成了原理样机的研制。
On this basis, the principle prototype is developed with high speed digital signal processor (DSP), the huge reprogrammable logic gate arrays (FPGA) and real-time software.
在此基础上，采用高速数字信号处理器、大规模可编程逻辑门阵列和实时软件进行系统设计，完成了原理样机的研制。
This paper presents a fine-grained pipeline algorithm for lu decomposition with column partial pivoting and gives the description of its implementation on field-programmable gate arrays (FPGA).
提出了一种可以进行列主元选取的细粒度lu分解流水线算法并在现场编程门阵列(FPGA)上得到了实现。
The gated silicon field emitter arrays (FEA) with small gate aperture have been successfully fabricated by dry etching, including ion beam etching (IBE) and reactive ion etching (RIE).
利用离子束刻蚀(IBE)和反应离子刻蚀(RIE)等干法刻蚀方法来制造带栅极的场发射阴极阵列。
The gated silicon field emitter arrays (FEA) with small gate aperture have been successfully fabricated by dry etching, including ion beam etching (IBE) and reactive ion etching (RIE).
利用离子束刻蚀(IBE)和反应离子刻蚀(RIE)等干法刻蚀方法来制造带栅极的场发射阴极阵列。
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