The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.
用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。
The optimized design of pipeline control unit is also proposed, which greatly minimizes the FSM states from 85 down to 23, with improvement in circuit speed and area utilizing.
其中，提出了流水线控制单元的优化设计，将控制状态机的状态数目从85个减少到23个，节省了电路面积，提高了速度。
The relationship of the steering range of FSM and the errors corrected, the detector output and objective error, tracking control system input are analysed.
并分析了反射镜作用范围与需要校正的误差的关系，跟踪探测器输出误差信号与物方跟踪误差，以及与跟踪镜控制量的关系。
The architecture and logical design of ingress process module, which includes receive control FSM, send control FSM and cell position adjustment logic;
通信协议转换逻辑上行方向的系统分析及体系结构设计，包括上行接收状态机、发送状态机、信元内字节位置调整机制等的设计；
The architecture and logical design of ingress process module, which includes receive control FSM, send control FSM and cell position adjustment logic;
通信协议转换逻辑上行方向的系统分析及体系结构设计，包括上行接收状态机、发送状态机、信元内字节位置调整机制等的设计；
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