The clock measures the passage of time in millionths of a second by counting the frequency of electromagnetic waves.
这种钟表通过电磁波的频率来计算时间，单位为百万分之一秒。
This is the basis for the well - known cesium clock, presently the standard of frequency and time.
这就是众所周知的铯原子钟的基础，它是目前的频率和时间基准。
A new tool that can test the clock base frequency error of energy measuring devices and provide GPS standard time to calibrate real-time clock was introduced in this paper.
介绍了一种用来测量电能计量装置的时钟基频误差，并提供GPS标准时间以校准其实时时钟的新型工具。
And it presents a efficacious method to enhance precision of real time control, which changes value of clock interrupt frequency by changing divided frequency of system tinier.
同时给出了一种提高实时控制精度的有效方法，即通过改写系统定时器的分频值达到改变定时器时钟中断频率的值。
The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency.
由于采样速率、滤波器转折频率、建立时间、群延迟和输出字速率与外部时钟频率呈比例变化关系，因此这些参数也会相应降低。
The clock offset and frequency drift rate for sensor nodes are estimated and then compensated by using the time-stamp recorded in two adjacent synchronizations.
该算法利用连续两次同步过程中所记录的时间信息来估算节点时钟的偏移和频率漂移率，并进行补偿。
Input clock frequency of 500hz, the time for lights between 1-4 seconds, they can control.
输入时钟频率为500hz，灯亮的时间在1—4秒之间，可以自由控制。
Based on pulse counting principle, the high precision time interval can be obtained by measuring the number of the high-frequency reference clock through it.
设计了一种高精度时间间隔测量模块，该模块由单片机控制，采用脉冲计数原理，通过测量时间间隔内高频参考时钟个数，得到被测时间间隔的精确值。
Based on available frequency standards: one prototype laboratory model of cesium clock, three hydrogen clocks and several (2-6) rubidium clocks, the SO atomic time scale has been established.
利用我们现有的标准，一台试验型实验室铯束标准，三台氢原子钟以及若干台(2 -6)铷气泡标准来建立原子时尺度。
Simulation results show the PLL clock frequency multiplier has lower phase noise and shorter capture time.
结果表明，PLL倍频器具有较低的噪声和较高的捕获速度。
Adding parallelism typically increases gate count, but the improved computational efficiency allows for the lower clock frequency needed to meet real-time constraints.
添加并行一般通过门数增加来实现，但提高计算效率要求降低时钟频率以满足实时需求。
Based on Gaussian random process model and continuous-time system in time domain, this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
Based on Gaussian random process model and continuous-time system in time domain, this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
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