The clock measures the passage of time in millionths of a second by counting the frequency of electromagnetic waves.
这种钟表通过电磁波的频率来计算时间，单位为百万分之一秒。
This is because process execution now needs to be coordinated across the bus, which operates at half the clock frequency of the chip.
这是因为进程执行现在需要跨总线协调，以一半的芯片时钟频率进行处理。
The numbered, it reflects various characteristics such as smoothness of engraving, the amount of memory cache, frequency of buses required, or clock speed.
编号的，它反映了不同的特色，如光滑的雕刻，金额内存高速缓存，频率巴士的要求，或者时钟速度。
This is the basis for the well - known cesium clock, presently the standard of frequency and time.
这就是众所周知的铯原子钟的基础，它是目前的频率和时间基准。
This makes possible to control the plural flows of data even with the considerable increase for clock frequency.
这使得能够控制复数流动的数据，甚至与相当的增加时钟频率。
This article mainly addresses the maintenance period of clock frequency of SPC exchanges in China's telecommunication network.
本文主要讨论我国电信网中程控交换局时钟频率维护周期的确定问题。
Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
This paper introduces the frequency deviations of NIM4 Cesium fountain clock , the method and result of a new evaluation.
详细介绍NIM4铯喷泉钟系统频移及其不确定度的最新评定方法和结果。
A new tool that can test the clock base frequency error of energy measuring devices and provide GPS standard time to calibrate real-time clock was introduced in this paper.
介绍了一种用来测量电能计量装置的时钟基频误差，并提供GPS标准时间以校准其实时时钟的新型工具。
This paper introduces the method of clock calibration to VCXO in system, based on GPS and CPLD. It can solve the problem of frequency offset because of Crystal worse behavior in Long-term use.
本文还给出了基于GPS芯片和CPLD，对系统压控晶振时钟进行校准的实现方法，有效解决了由于长时间使用，晶振自身特性变化，造成的频率偏移现象。
The capacity and speed of the memory subsystem in this architecture can be improved using the existed memory devices while the cost can be downgraded without enhancement of the clock frequency.
该结构可利用现有存储器件在不增加时钟频率的情况下，提高存储器系统的容量和速度，同时降低成本。
Therefore, the clock frequency directly affect the speed of MCU, clocking circuit and the quality of directly influence the stability of single-chip microcomputer system.
因此，时钟频率直接影响单片机的速度，时钟电路的质量也直接影响单片机系统的稳定性。
Absrtact: Along with the increase of digital system working frequency, clock period gets shorter, timing of the system becomes more complex.
摘要：随着数字系统的工作频率的不断提高，时钟周期逐渐变小，而系统时序却越来越复杂。
The conversion speeds and results of ADC0809 analog-to-digital converter are accurate tested and analyzed by using multi-master clock pulse with different frequency and pulse width.
使用多组不同频率和不同脉宽的工作时钟，定量测定分析ADC0 80 9模数转换器的转换速度和转换结果。
In this case, the crystal oscillator can not provide a stable clock frequency, which results in the abnormality of the device.
在这种情况下，晶体振荡器就不能为设备提供稳定的时钟频率，导致设备工作异常。
This will allow NVIDIA to raise the maximum clock frequency of memory from present 1800 MHz to 2200 MHz.
这将使NVIDIA的提高，最高的时钟频率的内存，从目前的1800兆赫到2200兆赫。
A frequency comparator compares the frequency of a reference clock with that of an output clock and outputs a frequency comparison signal.
频率比较器比较基准时钟和输出时钟的频率，并输出频率比较信号。
A second reason why clock frequency will no longer be an accurate measure of performance is that distributing the clock's signal to all the different parts of a chip is more difficult that it sounds.
时钟频率不再是性能的精确测量指标的第二个原因是，将时钟信号分配到芯片的不同部分，要比说说困难得多。
By analysing frequency spectrum in this paper, we can understand that when NRZ code be transferred into RZ code of 1/2 mark-to-space ratio, the timing clock can be obtained at largest power.
本文通过对NRZ、RZ伪随机码序列进行频谱分析，得知当NRZ码变换成码元占空比为1/2的RZ码时，所提取出的定时时钟功率最强。
Based on pulse counting principle, the high precision time interval can be obtained by measuring the number of the high-frequency reference clock through it.
设计了一种高精度时间间隔测量模块，该模块由单片机控制，采用脉冲计数原理，通过测量时间间隔内高频参考时钟个数，得到被测时间间隔的精确值。
The loop design of the passive atomic clock is discussed to accomplish the transfer of the frequency accuracy and stability from the atomic resonance to the locked oscillator.
本文就被动型原子钟的环路设计讨论了原子谐振器频率准确度和稳定向锁定晶振的传递问题。
The paper introduces the principle of PLL clock synthesizer and the structure of MC12429, designs the circuit of the High Frequency clock synthesizer.
本文介绍了PLL合成时钟源的原理，介绍了MC 12429的结构，设计出了高频时钟源电路图。
The clock transition frequency and linewidth of the clock transition line were obtained by scanning the microwave frequency in a narrow region.
通过减小微波扫描的频率范围，得到钟跃迁频率和谱线线宽。
And the selection and design of switch-in module, switch-out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed.
论文中还给出了开关量输入、开关量输出、通信模块、时钟电路、数据存储器、按键电路和频率跟踪电路等各功能模块的选择方法和设计原理。
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。
Based on available frequency standards: one prototype laboratory model of cesium clock, three hydrogen clocks and several (2-6) rubidium clocks, the SO atomic time scale has been established.
利用我们现有的标准，一台试验型实验室铯束标准，三台氢原子钟以及若干台(2 -6)铷气泡标准来建立原子时尺度。
Input clock frequency of 500hz, the time for lights between 1-4 seconds, they can control.
输入时钟频率为500hz，灯亮的时间在1—4秒之间，可以自由控制。
The delay circuit is used for both frequency and phase adjustments of the output clock.
延迟电路可通用于输出时钟的频率调整以及相位调整这两方面。
The delay circuit is used for both frequency and phase adjustments of the output clock.
延迟电路可通用于输出时钟的频率调整以及相位调整这两方面。
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