The FLL features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
在FLL功能数字频率锁定环(FLL)的硬件，与数字调制器，稳定会计频率可编程多的观赏晶体频率。
Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).
然后介绍了锁相环(PLL)的基本结构、相位模型、频率响应、噪声及杂散性能。
The loop design of the passive atomic clock is discussed to accomplish the transfer of the frequency accuracy and stability from the atomic resonance to the locked oscillator.
本文就被动型原子钟的环路设计讨论了原子谐振器频率准确度和稳定向锁定晶振的传递问题。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
本文分析了数字锁相环路的寄生频偏，它是现代通讯系统中频率合成器的重要指标之一。
Through debugging the hardware circuit of the Phase Locked Loop and writing the Single-Chip Processor program, a good performance frequency source is realized.
通过对锁相环硬件电路的调试和编写相关单片机控制程序，实现了一个性能较好的频率源。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
All digital Phase-Locked Loop frequency tracking and digital SPWM realization technology based on FPGA are emphasized in the research.
重点研究了基于FPGA的全数字锁相环频率跟踪技术和数字化SPWM实现技术。
This paper will discuss a new way to speed frequency hopping of frequency synthesizer. This way will assure that loop circult is locked in a very short time.
本文介绍一种加快频率合成器跳频速度的新方法，该方法能确保环路的初始频差在快捕带以内，使环路迅速捕获锁定。
In the system, we adopt a balance channel frequency offset structure, phase locked IF tracking technique and opened loop precorrection.
在系统结构上采用了平衡通道频率补偿技术、中频锁相跟踪技术和开环预校正技术。
The phase locked loop (PLL) frequency synthesizer for digital tuning system(DTS), which is used in DTS of car radio receiver, is presented.
针对一个汽车音响收音数字调谐系统的实例，介绍了一种广播用双波段锁相环频率合成芯片的设计方法。
The principle of voltage linear digital triggering of thyristor by EPROM is described and it is discussed to solve the frequency disturbance on digital trigger by phase locked loop .
描述了用EPROM实现晶闸管电压线性触发原理，讨论了用锁相环解决数字触发的频率扰动问题。
Introduces the basic principle of phase-locked loop and NE564 PLL circuit structure and properties, and the use of phase-locked NE564 demodulating circuit and phase-locked frequency circuit.
介绍了锁相环的基本原理和锁相环ne564的电路结构和性能，及其用ne564构成的锁相解调电路和锁相倍频电路。
The phase-locked system is a closed loop automatic control system that can follow the frequency and phase of the input signals.
锁相系统是一个能够跟踪输入信号频率和相位的闭环自动控制系统。
High precise measuring and tracking of carrier frequency-deviation is necessary to the realization of a high performance phase locked loop in carrier recovery.
载波恢复中高精度的频偏检测与跟踪是高性能锁相位环路实现的必要条件。
The simulation results prove that the three-phase phase-locked loop can work well in disturbance situation and variable frequency system when the frequency of the inputs is variable.
并对相位突变和频率突变的情况进行了仿真研究，说明在相位和频率发生变动时三相锁相环仍能有效地锁定相位，能够满足系统变频的要求。
The industrial grating signals can be digital frequency multiplication with a phase-locked loop (PLL) controlled by a microcomputer.
用微型计算机控制锁相环(PLL)可对计量光栅信号进行数字倍频。
The phase- locked loop is one kind of control system which is able to achieve phase automatic lock, to compose frequency and to trace demodulation system.
锁相环路是一种能实现相位自动锁定的控制系统，主要用于频率合成及跟踪解调系统。
In the process of signal digital intermediate-frequency received, digital down convertion, frequency tracking of carrier and phase locked loop are the keys.
在信号的中频数字接收过程中，数字下变频、载波频率与相位跟踪是设计的关键所在。
The paper studies digital control scheme of resonance inverter frequency-tracking based on all digital phase-locked loop.
本文主要研究了基于全数字锁相环的谐振型逆变器频率跟踪的数字化控制方案。
After attaining synchronization, the phase offset due to frequency offset estimation error is tracked with a phase locked loop.
同步捕获后则通过锁相环技术跟踪长突发的同步变化。
Furthermore, the working principle and phase noise of frequency-locked loop are analyzed and discussed in this paper.
给出了实验结果，并对锁频环的工作原理、相位噪声进行了分析和讨论。
Signal demodulation of automatic block with audio frequency shift modulated track circuits was implemented with phase-locked loop (PLL) technique and a singe chip microcomputer.
利用锁相环(LL)窄带跟踪特性，与单片机结合，实现自动闭塞系统移频信号解调。
A novel Frequency and Phase Tracking Locked Loop (FPTLL) is proposed in this paper.
本文介绍了一种新型频率相位追踪锁定环路（FPTLL）的设计。
The phase-locked loop frequency synthesizer is a kind of phase lock installment and it is a kind of separate gap frequency code generator with high stability frequency.
锁相环频率合成器是一种相位锁定装置，是一种频率稳定度较高的离散间隔型频率信号发生器。
Now the full integrated PLL (phase locked loop) chip is used widely in radio frequency circuit.
全集成锁相环芯片目前在射频电路中应用很广泛。
The use of phase-locked loop technology makes the sampling frequency synchronously follow the signal frequency and improves the calculation accuracy of sampling data.
运用锁相环技术使采样频率同步跟踪信号频率，提高采样数据计算的准确性。
The chapter 4 discuss some question of the circuit using programmable device like digital phase locked loop and digital frequency multiplier, it can increase the way of circuit design.
第四章探讨了运用可编程技术设计数字锁相环和数字倍频器的相关问题，为以后电路设计拓展更多的方法。
In the electronic instrumentation aspect, the phase-locked loop in instruments and so on in frequency synthesizer and phase meter played the vital role.
在电子仪器方面，锁相环在频率合成器和相位计等仪器中起了重要作用。
Project 1 will be focused on the design and SPICE simulation of a high speed frequency divider for phase-locked loop applications.
专题1主要是讨论用于相锁迴路应用的高速分频器设计和SPICE模拟。
In this dissertation, theory, model, design and implementation of charge pump phase locked loop frequency synthesizer are lucubrated.
本文围绕电荷泵频率合成器的理论、模型、设计和实现，进行了深入的研究。
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