The FPGA decompresses the data stream, accelerating it by up to eight times.
FPGA解压数据流，可以将速度提升高达8倍。
You've now downloaded and started your first PowerPC program inside an FPGA.
现在已经在FPGA内下载并启动了您的第一个PowerPC程序。
For development purposes, you can load the FPGA directly from a host PC over a JTAG interface.
就开发目的而言，可通过JTAG接口直接从主机PC加载FPGA。
The usual method is to include a tiny program inside a piece of block ram (BRAM) within the FPGA bitstream.
通常的方法是在fpga比特流中的一段块ram (BRAM)内包含一个小程序。
You would probably not choose this method for a system where the FPGA itself is going to be the main processor.
如果系统中fpga本身将作为主处理器，则不应该为该系统选择此方法。
Implement the channel out-coding based on FPGA.
完成信道外编码的FPGA实现与验证。
The acquisition controller is redesigned by applying FPGA chip.
用FPGA芯片对采集控制器重新设计。
The loading mode and process of programmable data of FPGA device are discussed.
探讨现场可编程门阵列（FPGA）器件编程数据的装载模式及过程。
This paper mainly introduced raster displacement detection system based on FPGA.
本论文主要研究基于FPGA的光栅位移检测系统。
Having the "right" team will have a significant impact on an FPGA project's efficiency.
拥有“最合适”的团队会对FPGA项目的效率产生显著的影响。
A design method of a driving circuit for flat panel display based on FPGA is introduced.
介绍了一种基于FPGA的平板显示器件驱动电路的设计方法。
In view of this, the thesis designs a low cost, portable, easy to learn and extend FPGA studying board.
论文正是基于以上考虑，设计了一种成本低、简单易学、便于携带和扩展的FPGA实验板。
Example analysis shows that the method is simple and effective and can make FPGA design more convenient.
实例分析表明，该方法简单有效，可为FPGA设计带来极大的方便。
Hardware random number generator in the FPGA interface is used to accelerate the evolutionary algorithm.
FPGA接口中的硬件随机数发生器实现进化算法的硬件加速。
Chapter five briefly introduces the implementation of system software including DSP, FPGA and PC control Programming.
第五章介绍了系统的软件实现，包括了DSP程序，FPGA程序和主机程序。
So a digital real time system for radar signal acquisition and processing is designed by the chip of FPGA and DSP in this paper.
针对这一问题，本设计利用FPGA和DSP芯片，设计了一个数字化的雷达原始信号采集与处理的实时系统。
This chapter stresses the importance of a defined, efficient and optimized FPGA design process for rapid system development efforts.
这一章强调了定义清晰的、高效的和优化的FPGA设计过程对快速系统开发工作的重要性。
Before writing the logic design of FPGA to the chip, we usually use some EDA tools to simulate and test logical functions of the design.
在设计写入FPGA芯片之前，通常运用EDA工具对其逻辑功能进行充分模拟和测试。
Hence, FPGA fault tolerant design technology must be developed to make up for the insufficiency in radiation resistance of its components.
在面向航天应用的FPGA设计中，必须采用容错设计技术来弥补器件本身抗辐射能力的不足。
Therefore the research of high-speed data acquisition and real-time processing based on the combination of FPGA and ARM is of great significance.
因此进行基于FPGA与ARM相结合的高速数据采集与实时处理的研究具有重要的意义。
Later, you can migrate various parts of the application into virtual "hardware" inside the FPGA, thereby freeing up CPU resources for other tasks.
随后，可将该应用程序的各部分迁移到FPGA中的虚拟“硬件”，从而释放CPU资源供其他任务使用。
In a nutshell, the principal benefit of the FPGA is unparalleled design flexibility as to where you place the border between hardware and software.
简单地说，FPGA的主要益处就是，它可在确定软、硬件的界限方面展现出空前的设计灵活性。
The FPGA then filters out any data not relevant to the query, streaming the remaining data back to memory for concurrent processing by the CPU core.
FPGA然后过滤掉与查询无关的数据，将剩余的数据放回内存，供 CPU 内核进行并发处理。
VHS-ADC, a high-speed signal processing system based on FPGA, has been applied widely in communication, audio, video and radar signal processing fields.
VHS-ADC是一种基于FPGA的高速数字信号处理平台，在通信、音视频、雷达信号处理等领域得到了成功的应用。
This paper presents a hardware structure-independent weight-based fault injection model for accurate emulation of the radioresistance in the SRAM-based FPGA.
提出一种与具体硬件结构无关、基于权重的错误注入模型，用于准确模拟基于SRAM的现场可编程门阵列抗辐射性能。
The idea is that you include this "halt and wait" code in the BRAM so you can configure the FPGA, then attach a debugger and download the code you want to run.
该理念是在BRAM中包含此“haltandwait”代码，这样就能配置FPGA，然后附上一个调试器并下载想要运行的代码。
The reality of the situation is that the programmability of an FPGA makes it inherently larger (in terms of transistor count) than an equivalent hardwired chip.
真实的情形是，FPGA的可编程性使它天生就比同等的硬布线芯片大(就晶体管数量而言)。
Having a defined FPGA design process helps reduce the number and impact of design errors on a rapid development project by providing a development control mechanism.
定义清晰的FPGA设计过程通过提供一个开发过程控制机制，有助于减少设计错误的数量和减轻设计错误对快速开发项目的影响。
Note that you can actually instantiate more than one processor inside the FPGA (the Virtex-4 supports two PPC405 cores), but the wizard doesn't support such designs.
请注意，实际上您可在FPGA中实例化多个处理器(Virtex - 4支持两种PPC405核心)，但向导不支持这种设计。
Note that you can actually instantiate more than one processor inside the FPGA (the Virtex-4 supports two PPC405 cores), but the wizard doesn't support such designs.
请注意，实际上您可在FPGA中实例化多个处理器(Virtex - 4支持两种PPC405核心)，但向导不支持这种设计。
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