NOR flash memory can typically be programmed a byte at a time, whereas NAND flash memory must be programmed in multi-byte bursts (typically, 512 bytes).
NORflash内存通常一次可以编写一个字节，而NAND flash内存必须编写多个字节(通常为512字节)。
These programs reside in special region of flash memory on the target hardware and provide the means to download a Linux kernel image into flash memory and subsequently execute it.
这些程序位于目标硬件上的闪存中的某一段特殊区域，它们提供了将Linux内核映像下载到闪存并继续执行的方法。
However, many other types of memory are RAM as well (ie, Random Access memory), including most types of ROM and a kind of flash memory called NOR-Flash.
然而，许多其他类型的内存以及内存(即随机存取记忆体)，其中包括大多数类型的ROM和一种所谓的NOR快闪记忆体闪光。
Such a flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one bit of data.
这种快闪存储器装置有时称为二元快闪存储器装置，因为每个存储器元件可存储一个数据位。
This paper introduces the structure and attributes of flash memory. And the digital camera system based on NAND flash memory is then presented and described.
该文分析了目前常用的快闪存储器的结构和特性，在此基础上介绍了基于NAND闪存的数码相机系统。
The embodiment of the invention realizes the functions of the flash memory and a read only memory on a chip of the flash memory, and the cost is reduced.
本发明实施例方案在一片闪速存储器芯片上实现了闪速存储器功能和导入只读存储器功能，降低了成本。
A flash memory integrated circuit includes a plurality of flash memory arrays.
快闪存储器集成电路包含多个快闪存储器阵列。
The method can ensure that the data can be completely written on a data piece of the flash memory and can not be lost due to the quality problem of the flash memory.
本发明的方法可以保证数据都写在完好的闪存数据块上，保证了数据不会因为闪存的质量问题而丢失。
The invention provides flash memory equipment, a method and a system for managing a flash memory, which relate to the filed of semiconductor memory media.
本发明涉及半导体存储介质领域，提供了一种闪存设备、闪存管理方法及系统。
An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with a duplicity of data registers and a controller circuit.
一种改进的基于闪速EEPROM存储器的存储子系统，包括一个或多个闪存阵列，每一个都带有两个数据寄存器和一个控制器电路。
An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with a duplicity of data registers and a controller circuit.
一种改进的基于闪速EEPROM存储器的存储子系统，包括一个或多个闪存阵列，每一个都带有两个数据寄存器和一个控制器电路。
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