In this paper, we discuss a FIFO memory electrocircuit, which is designed from the top down and have been fabricated successfully.
文中的设计思想和具体的逻辑电路可以通用于所有先进先出存储器的设计。
The system controls the logic of the data acquisition board by programmable logic device (PLD) with the center of the ARM microcontroller and FIFO memory and provides the simulate waveforms.
系统以ARM微处理器和FIFO存储器为核心，利用可编程逻辑器件实现对整个底层数据采集系统的逻辑控制，并给出了时序控制部分的仿真波形。
The new method improves the efficiency of bus and reduces the size of frame buffer in memory and FIFO in DMA channel.
这种结构提高了总线效率，并且减小了内存中解码帧缓冲器和通道中FIFO的面积。
In data storage transmission modular, we adopt PCI bus line and FIFO data memory carry out succession for plenty of data to storage transmission, guarantee AE signal accurate collecting.
数据存储传输模块采用PCI总线和FIFO数据存储器对大量的数据进行连续存储传输，保证数据的准确完整。
This FIFO receiver buffer receives data at an input write-data rate filling up the memory storage cells therein.
这先进先出接收机接收缓冲区写在输入数据速率的内存填补其中的数据存储单元。
Instead of using block memory, this design employs distributed memory to hold the data in FIFO.
替代使用的阻塞存储器，本设计在FIFO中使用分布式存储器保存数据。
The interface uses a circuit based on dual port FIFO buffer memory to realize data transfer of different I/O velocity between the two computers.
该接口采用双端口FIFO缓冲存储技术，实现两机间不同I／O速度的数据通信。
When a new fingerprint is found, a first-in first-out (FIFO) strategy is used to allocate space in a limited memory-space to store the new entry.
当发现一个新的指纹时，使用“先进先出(FIFO)”策略在有限的存储空间中为存储新的条目分配空间。
When a new fingerprint is found, a first-in first-out (FIFO) strategy is used to allocate space in a limited memory-space to store the new entry.
当发现一个新的指纹时，使用“先进先出(FIFO)”策略在有限的存储空间中为存储新的条目分配空间。
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