The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic.

这款双通道adc内核采用多级、差分流水线架构，并集成了输出纠错逻辑。

youdao

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic.

这款双通道adc内核采用多级、差分流水线架构，并集成了输出纠错逻辑。

youdao