This paper presents a design technology from a compilation view for embedded DSP processors. Under the guidance of this method, it designs a 16 bits DSP core.
从编译的角度对嵌入式DSP核提出了设计方法，并用此方法设计了16位定点DSP核。
This paper presents a design technology from a compilation view for embedded DSP processors. Under the guidance of this method, it designs a 16 bits DSP core.
从编译的角度对嵌入式DSP核提出了设计方法，并用此方法设计了16位定点DSP核。
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