A double edge triggered counter is designed, and the redundancy attribute of the circuit is utilized to decrease the power consumption of the system.
设计了双边沿触发计数器，并利用电路的冗余特性，降低了系统的功耗。
Some new low-noise edge triggered flip-flops are presented, and their logic levels are realized in the current domain by steering a constant dc bias current.
提出以电流信号表示逻辑值的新型低噪声触发器设计，用于高性能混合集成电路的设计中以减少存贮单元开关噪声对模拟电路性能的影响。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider.
提出了一种基于共振隧穿二极管的新型边沿触发d触发器并将之用于构成二进制分频器。
The MZM is driven by a non-return-to-zero (NRZ) data sequence and biased at the nonlinear point to generate edge-triggered pulses.
利用双输出口调制器典型的互补输出特性，通过偏置调制器于非线性传输点，可得到一对由NRZ序列边沿触发的明暗脉冲。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
The application of this type of double-edge-triggered flip-flop in seq…
文章还介绍了该双边沿触发器在时序电路中的应用。
Based on the construction of traditional flip-flop, we propose a novel edge-triggered flip-flip using one latch controlled by narrow pulse according to race-hazard of clock.
在传统触发器结构的基础上，本文提出了单闩锁结构边沿触发器设计，它通过利用时钟信号的竞争冒险产生窄脉冲控制单一锁存器以实现触发器的一次状态转换功能。
The ECL OR-AND-gate can simplify a generalized ECL circuits structures, for example, an ECL double-edge-triggered D flip-flop.
作为常规ECL门的补充类型，常可用于简化一般ECL电路结构，例如ECL双边沿D触发器。
Both of the timer LOGO! and STEP7 have the function of on-delay, off-delay, retentive on-delay and edge-triggered interval time-delay. LOGO!
和STEP7的定时器都具有接通延时、断开延时、保持接通延时、边缘触发延时和脉冲输出功能，LOGO！
Both of the timer LOGO! and STEP7 have the function of on-delay, off-delay, retentive on-delay and edge-triggered interval time-delay. LOGO!
和STEP7的定时器都具有接通延时、断开延时、保持接通延时、边缘触发延时和脉冲输出功能，LOGO！
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