To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.

从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。

youdao

To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.

从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。

youdao