Market prices for some types of DRAM chip rose today by around 7%.
部分类型的DRAM芯片的市场价格今天上涨了约7%。
Samsung expects to have more than 10 percent of its total DRAM chip production in 2012 at the 4gb (or higher) density.
据三星预计，2012年三星将有10%的内存芯片产品是基于4gb及更高容量密度的芯片。
Modern processor performance increases at a rat of 60% per year, while the bandwidth of a DRAM chip increase by only 15%-20% per year, with latency improved by only 7%.
现代处理器性能以60%的年增长率飞速发展，相比之下，处于不同工艺下的DRAM的时滞和带宽的改进却分别只有7%和15～20%；
Samsung has announced the world's highest density DRAM chip, a 4GB DDR3 module, which is manufactured using a 50nm technology and is double the size of previously available DDR3 chips.
三星宣布了世界上密度最高的DRAM芯片，4GBDDR3模块，以50纳米技术制造，为现有DDR3芯片容量的2倍。
Second-ranked computer memory chip maker Hynix Semiconductor and Japan's Elpida memory swung to deep losses as prices of DRAM chips used in PCs tumbled about 50 percent in the third quarter.
排在第二位的电脑内存芯片生产商海力士半导体和日本的尔必达存储器公司在电脑用DRAM芯片销售价格上损失惨重，在第三季度跌落50%。
Samsung was the sole profitable firm among major global dynamic random access memory (DRAM) chip makers in the third quarter.
在第三季度，三星公司是在全球动态随机存取记忆(DRAM)芯片制造商中唯一盈利的公司。
Sometimes, the contents of a ROM chip are copied to SRAM or DRAM to allow for shorter access times (as ROM may be slower).
有时，内容的光碟片复制到SRAM或DRAM芯片，以便缩短存取时间(如rom可能会比较慢)。
Opening the drive one can clearly see the Toshiba flash, Hynix DRAM that is the cache, and a chip that says Phison.
打开驱动器都可以清楚地看到东芝闪存，这是海力士DRAM缓存，芯片，上面写着群联。
The spokesman says Hailishi, the flexibility that we had stopped to so that raise us, sell DRAM memory chip through spot market and enhance us to be in the position of contract market.
海力士讲话人称，咱们已经遏制经由过程现货市场发卖DRAM内存芯片以便进步咱们的灵敏性和增强咱们在合同市场的地位。
This analyst is forecasted, about 20% what spot market takes market of chip of all DRAM memory.
这位分析师猜测，现货市场占全数DRAM内存芯片市场的大约20%。
DRAM is a semiconductor chip used in most electronic products such as personal computers.
动态随机存取记忆体是应用于电子产品的半导体晶片，如个人电脑等。
Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。
Experimental results also reveal two primary causes which make theoretical speedup hard to achieve: limited DRAM bandwidth and resource contention of on-chip network.
通过实验还证明实测性能难以达到理论预测值的两个主要原因：访存带宽有限和片上网络的资源竞争。
Experimental results also reveal two primary causes which make theoretical speedup hard to achieve: limited DRAM bandwidth and resource contention of on-chip network.
通过实验还证明实测性能难以达到理论预测值的两个主要原因：访存带宽有限和片上网络的资源竞争。
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