Double Edge Trigger counter is composed of odd counter, even counter and data selector.

双边沿触发计数器由偶数、奇数加法计数器及数据选择器组成。

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Data selector alternately to realize the functions of double edge trigger addition counter output the odd and even data in two counters.

数据选择器则将两个计数器中处于保持状态的奇偶数据交替输出，实现双边沿触发加法计数器的功能。

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To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.

从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。

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To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.

从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。

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