Combining the Constructivism Ideology and taking the case of digital clock design, this paper presents the Application of Constructivism Ideology in Embedded System course teaching.
结合嵌入式系统课程的特点，并以数字时钟的设计为例，介绍了将建构主义教学理论应用于嵌入式系统课程教学。
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
In this paper, multi-function digital clock system design.
本文介绍了多功能数字钟的系统设计。
Clock skew is in a synchronization digital integrated circuit design difficult problem.
时钟偏移是同步数字集成电路设计中的一个难题。
In designing synchronous digital integrated circuits, the design of clock tree is an important component, which may greatly affect the performance and reliability of the system.
时钟树的设计是同步数字集成电路设计中的一个重要部分，对系统的性能和可靠性有很大影响。
This paper introduces hardware constitution and software design of digital clock controlled by 8031 single-chip microcomputer, and its assembly language program is given.
介绍了用8031单片机控制的电脑数字钟的硬件结构与软件设计，给出了汇编语言源程序。
In this trend, digital clock, multifunction clock has become the modern design of the production of research-led direction.
在这种趋势下，时钟的数字化、多功能化已经成为现代时钟生产研究的主导设计方向。
This design is a simple digital calendar display system recording real-time calendar clock information.
设计了一种可以记录实时日历时钟信息的简易数码信息历显示系统。
The theory of operation, design considerations, design, characters, main features of model ST0202 high performance digital clock are described in this paper.
本文介绍ST0202高性能数字钟的设计出发点、工作原理、设计特点和主要性能。
This paper introduces the process of logic design of digital circuits, and mainly explains the function of asynchronous counter and decoder. The digital clock is an example of this application.
本文介绍了数字电路系统的逻辑设计过程，并且着重阐明异步计数器和译码器的功能，数字钟是这方面应用的一个实例。
It provides with a program design of the digital clock both on hardware and software in this paper.
因此，在此基础上进行了数字电子钟设计的工作，给出数字电子钟的软件和硬件的设计。
Design error in a millisecond years, free proof of the digital clock, minutes and seconds required with a display, power-down when the clock is running, free proof.
设计一个年误差在毫秒级、免校对的数字钟，要求带有时分秒显示、掉电时时钟正常运行、免校对。
The author introduces the design of digital display clock, the time signal received by GPS satellite receiver corrects time automatically after receiving and processing by single chip computer.
介绍一种利用GPS卫星接收机接收的时间信号，经单片机接收处理后进行自动校时的数显时钟的设计。
This paper discusses the design and implementation of a low-power digital clock chip.
本文讨论了一种低功耗时钟芯片的设计与实现。
For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.
在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。
For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.
在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。
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