The paper proposes a mew method for testing combinational digital circuit which is based on the VHDL language.
本文提出了一种新的基于VHDL语言的组合数字电路测试码自动生成方法。
The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance.
仿真实验结果证明了改进演化算法对于实现函数级数字组合逻辑电路的硬件演化是可行的，并且提高了演化算法的演化效率和收敛性能。
This experimental quide to the digital logic comprises two parts: combinational logic and sequential logic.
本实验指导书分为两大部分：组合逻辑，时序逻辑。
The paper also discusses the design principle of super-high-speed digital circuits and some examples of combinational and sequential circuits using linear AND-OR gate are given.
本文还讨论了应用线性“与或”门设计超高速数字电路的准则以及有关的组合和时序电路设计实例。
The paper also discusses the design principle of super-high-speed digital circuits and some examples of combinational and sequential circuits using linear AND-OR gate are given.
本文还讨论了应用线性“与或”门设计超高速数字电路的准则以及有关的组合和时序电路设计实例。
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