The paper introduces the method of using medium-scale integrated calculator core to design the arbitrary digit sequence pulse generator and gives examples to illustrate its application.
提出了利用中规模集成计数器芯片设计任意位数系列脉冲发生器的方法；并举例说明了应用。
The sample circuit samples an output of the decay circuit at a sample time after the decay circuit receives the pulse for the most significant digit.
采样电路在衰减电路接收到用于最高有效数字的脉冲之后的采样时间对衰减电路的输出进行采样。
The error in experimental determination of RTD derived from tracer pulse injection, digit time and response measurement, and flow model parameter estimation are discussed.
本文分析了用脉冲法注入示踪剂时示踪剂的分布、时间与应答信号的测量，以及模型参数的回归等方面的种种误差。
The pulse generator serially outputs pulses representing digits of a digital word least significant digit first.
脉冲发生器串行地输出表示数字字的数字的脉冲，首先是最低有效数字。
The pulse generator serially outputs pulses representing digits of a digital word least significant digit first.
脉冲发生器串行地输出表示数字字的数字的脉冲，首先是最低有效数字。
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